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FPGA Acceleration for the LoFreq variant caller

C 88.02% Tcl 4.25% Makefile 7.72%
bioinformatics bioinformatics-tool fpga hls lofreq xilinx probability-distribution variant-calling poisson-binomial-distribution vitis-hls

lofreq-fpga's Introduction

Overview

This repo is for research artifacts of paper "An FPGA Accelerator for Genome Variant Calling" published at FCCM 2022.

The paper presents an FPGA-based accelerator of LoFreq which runs 30X faster than the multiprocess CPU baseline. The figure below shows the speedup on 7 SARS-CoV-2 datasets. The speedup mainly results from multiple levels of parallelization and pipelining.

The dataflow of LoFreq's key algorithm (Possion Binomial Distribution) is shown in the figure below. The number of Outer Loop Iterations is commonly several million. (More details can be found here.) Straightforward parallelization is prevented due to the data dependency. Our FPGA accelerator achieves massive speedup from exploiting multiple levels of parallelism:

  • Processing multiple data in parallel
  • Parallelizing memory access, logarithm pre-compute, and inner loop iterations
  • Parallelizing and pipelining inner loop iterations

Moreover, a design space exploration is carried to decide the parallelization factor at each level in order to achieve the best performance given finite resources. The figure above shows results for four points in this design space, among which Design 3 is the best.


Source Directory

├── Makefile: commands to build .xo and .xclbin.
├── README.md
└── src 
    ├── Makefile: commands to run Vitis HLS sythesis.
    ├── hls.tcl: tcl script to set up and run HLS C sythesis.
    ├── krnl.c: HLS C source code.
    ├── krnl.h: header file.
    ├── runPre.tcl: building configuration.
    └── u250-krnl.cfg: Vivado implementation strategy control and SLR connectivity specification.

How to Build

  1. Make sure Xilinx Vitis is installed.
  2. Change configurations in Makefile or src/u250-krnl.cfg if necessary.
  3. Run make xclbin. For Vitis 2021 or prior versions, consider running make xclbin using faketime with a timestamp earlier than 20220101.

Citation

Please consider citing our paper if you find the paper/code useful. :)

@INPROCEEDINGS{9786183,
  author={Xu, Tiancheng and Rixner, Scott and Cox, Alan L.},
  booktitle={2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, 
  title={An FPGA Accelerator for Genome Variant Calling}, 
  year={2022},
  volume={},
  number={},
  pages={1-9},
  doi={10.1109/FCCM53951.2022.9786183}}

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