rj45/rj32

A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

rj32's Issues

Program memory waiting

Similar to #7

Support waiting potentially multiple cycles for program memory fetch to complete. Bonus if single cycle access is still supported. Should use ready/valid handshake.

This will unlock executing from potentially slow memory. It may also make it possible to have shared program and data memory.

Byte access to data memory

Implement the loadb and storeb instructions to load/store sign extended bytes.

Make the load and store instructions take byte addresses. The least significant bit will be ignored.

Implement new revision of the instruction set

In the new revision, the number of different immediate lengths has been reduced and room has been made for the imm instruction. There's also a spare bit on most instructions that might be useful in the far future.

are you still working on that great project?

Implement add/sub with carry

Implement addc and subc which set a temporary carry flag that causes the next instruction to take the carry output as an additional input. These should be not be interruptible via #11

Implement imm instruction

Add the imm instruction to carry the top 12 bits into the immediate of the next instruction. Add this as an automatic option to most instructions in the assembler using asserts.

Funnel shifter

Add a 32-bit funnel shifter able to shift up to 16 positions rightward. No left shift will be necessary.

Shift amount should come from an internal register.

The 32-bit input will be one of:

• a sign extended register for implementing asr
• a zero extended register for implementing shr
• a register with zero for shl
• or two different registers for ror / rol or multi-precision shifts

The internal shift amount register can be set from a register or immediate, and be set to either a N or 16-N.

Verilator simulation with video

It would be nice to be able to run the simulation a bit faster with verilator as opposed to only having the Digital simulation.

Bonus points if the video works and will display in a window.

VGA front panel microcode

The current character bus design in the VGA front panel is ....

Too long. Let's use the debug bus in #2 and build a small microcoded single-purpose state machine for drawing the frontpanel on the screen. Or it could be drawn into a text framebuffer. Not entirely sure yet.

Data memory waiting

Allow the processor to take multiple cycles to complete a memory read or write, controlled by a busy signal from the memory controller.

Should use a valid/ready handshake. Bonus points if same-cycle access is still supported.

Uninterruptible instructions

In #10 interrupts are implemented, but some instruction pairs lose their state if interrupted. Implement a temporary flag from the microcode that will not allow an interrupt to happen, which is cleared after the next instruction.

The imm instruction and addc/subc would set this flag.

Jump and Link / Function Calls

Need to implement a call or jump and link (jal) instruction in order to allow function calls. The return address should be put into register 15.

Interrupts

A single line can interrupt and cause the processor to jump to a specific address.

Debug bus

The CPU and front panel continue to grow inputs and outputs used only for debugging and are starting to get pretty hairy.

It would be better to have a debug bus that's implemented inside the CPU. The Digital front panel, vga front panel, and possibly a uart would all interact with this bus to pull the internal state.

The design could be similar to the ZipCPU's debug bus, but preferably simpler. Just an address, data, ready and valid. Each register and bus is available at an address, and the control signals are bundled into one or more 16-bit words.

Could contain a shadow copy of the register file by tying into any register file writes, this would allow reading the registers while the CPU is running.

Extend register file to 16 registers

Title says it all. Perhaps consider using the Digital register file component.