Sorry, if this is an offtopic, i'll move it to maillist if it's so. This is just common suggestions about "full metal runtime.js/nodejs" related to this #42 and this #43 issues.
Besides all features we all like JS because it is dynamic language. We can modify runtime environment during programm execution, create functionality on the fly, modify it, pass functions as parameters to the functions and so on. And now JS-driven technologies comes close to hardware layer of computing systems. Why not to try to combine dynamic software with dynamic hardware? I mean such technologies as FPGA (Field-programmable gate array) and PSoC (Programmable System on a Chip) i.e. Reconfigurable computing.
First I would like to quotate article about Intel experience in using combined server systems with Intel Xeon and FPGA modules: Intel unveils new Xeon chip with integrated FPGA, touts 20x performance boost.
Late yesterday, Intel quietly announced one of the biggest ever changes to its chip lineup: It will soon offer a new type of Xeon CPU with an integrated FPGA. This new Xeon+FPGA chip will fit in the standard E5 LGA2011 socket, but the integrated FPGA will allow each chip to be customized to specific workloads.
What’s the purpose of this new Xeon+FPGA product? In the words of Intel: “The FPGA provides our customers a programmable, high performance coherent acceleration capability to turbo-charge their critical algorithms.” Intel estimates that the Xeon+FPGA will see massive performance boosts in the 20x range (for code executed on the FPGA instead of a conventional x86 CPU — but obviously there will be big overall speedups as bottlenecks are removed. The other advantage is that workloads change — so if your critical algorithms change, or your whole company pivots, the FPGA can be repurposed without having to buy lots of new hardware.
So, for server applications this approach shows very good experimental results. With help of reconfigurable and programmable hardware we can implement device drivers, media codecs, network protocols, OS modules, crytical applications algorythms, additional devices and many other things.
Probably it is possible to make even "full-metal" V8 engine as CPU core, but probably this has no much sense, because hardware processor and dynamic interpreter is quite different things. I've herd about hardware implementations of systems like Forth, for example (it is also programming language, interpreter and operating system in one), when forth interpreter implemented as CPU core, but, looks like this is not very popular application. So it is possible to use all power of programmable MPSoCs in combination with compiled V8 core and additional core and applications modules, implemented programmatically or as a hard logic (as additional PCI devices, for example, or as modules with direct access to builtin CPU cores cache).
Intel used in their combined systems FPGA from Altera. As I can see more suitable for runtime.js system is All Programmable MPSoCs from Xilinx.
There are two series of Programmable SoCs form Xilinx: currently available Zynq-7000 AP SoC and newest series - Zynq® UltraScale+™ MPSoC. The short description with architectures schemas of UltraScale can be found in this article - Xilinx Introduces Zynq UltraScale+ MPSoC with Cortex A53 & R5 Cores, Ultrascale FPGA, technical details can be found here Zynq UltraScale+ MPSoC
Product Tables and Product Selection Guide
Here I'll describe in details some Zynq-7000 applications.
Zynq-7000 All Programmable SoC Overview
A high-level block diagram of the Zynq-7000 AP SoC is shown in Figure:
Each ARM Cortex-A9 processor has two 32 KB built-in level-1 caches for instructions and data, respectively. Another 512 KB on-chip level-2 cache is shared by the two processors. The snoop control unit (SCU) maintains the coherency of the caches in the two processors. The interconnection between the processor system and programmable logic is achieved through nine distinct AXI ports. The S_AXI_GP slave ports are typically used by the programmable logic that needs to access the processor system peripherals, while the M_AXI_GP master ports are mainly used by the processor system to access the register maps built in the programmable logic. The S_AXI_HP slave ports provide an efficient way for the programmable logic to access an external DDR memory or the 256 KB on-chip memory, while, for latency sensitive applications, the accelerator coherent port S_AXI_ACP offers direct accesses to the caches via the SCU. For a more detailed description of the Zynq-7000 AP SoC.
Wireless Base Station ZUC Block Cipher Implementation on Zynq-7000 AP SoC
This AP SoCs now available as SoM (System on Module) from Avnet - Zynq-7000 All Programmable SoC Systems:
From my point of view the most suitable for small cloud-enabled server module for runtime.js is MicroZed:
MicroZed™ is a low-cost System-On-Module, or SOM that is based on the Xilinx Zynq®-7000 All Programmable (AP) SoC. In addition to the Zynq-7000 AP SoC, the module contains the common functions and interfaces required to support the core of most SoC designs, including memory, configuration, Ethernet, USB, and clocks. On the bottom side of the module, MicroZed contains two 100-pin I/O headers that provide connection to two I/O banks on the programmable logic (PL) side of the Zynq-7000 AP SoC device. When plugged onto a user designed baseboard or carrier card, these 100-pin connectors provide connectivity between the Zynq-7000 AP SoC PL I/Os and the user circuits on the carrier card. MicroZed also includes onboard power regulation that can support a single 5 V to 12 V input.
Key Features
- SoC
- XC7Z010-1CLG400 or XC7Z020-1CLG400
- Memory
- 1 GB of DDR3 SDRAM
- 128 Mb of QSPI Flash
- Micro SD card interface
- Communications
- 10/100/1000 Ethernet
- USB 2.0
- USB-UART
- User I/O (via dual board-to-board connectors)
- 7Z010 Version: 100 User I/O (50 per connector) Configurable as up to 48 LVDS pairs or 100 single-ended I/O
- 7Z020 Version: 115 User I/O (58/57 per connector) Configurable as up to 55 LVDS pairs or 115 single-ended I/O
- Other
- 2x6 Digilent Pmod® compatible interface providing 8 PS MIO connections for user I/O
- Xilinx PC4 JTAG configuration port
- PS JTAG pins accessible via Pmod or I/O headers
- 33.33 MHz oscillator
- User LED and push switch
- Software
- Linux BSP and reference design
- Mechanical
- 4 inches x 2.25 inches (102 mm x 57 mm)
I think this could be very intresting perspective direction of porting runtime.js and nodejs/nodeos, because due to reconfigurable (dynamic) properties of this hardware it is possible to achieve very interesting results in server system performance, similar to Intel's ones.
Zynq-7000 contains Dual-Core 32-bit ARM Cortex-A9, Zynq UltraSCALE carries Quad-Core 64-bit ARM Cortex -A53.
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