shyamal-anadkat/wisc-sp13

CS 552 term project : functional design of a microprocessor called the WISC-SP13

WISC-SP13

CS 552 term project : functional design of a microprocessor called the WISC-SP13
Overview and specifications can be previewed here: http://pages.cs.wisc.edu/~karu/courses/cs552/spring2017/wiki/index.php/Main/ProjectDeadlinesAndGrading

wisc-sp13's Issues

Demo #1 - Unpipelined design (14% of project grade)

http://pages.cs.wisc.edu/~karu/courses/cs552/spring2017/wiki/index.php/Main/ProjectDeadlinesAndGrading

Project plan: (2% of project grade)

Each group needs to turn in a typed report (one to two page single-spaced) describing your project design and test plan. You are expected to develop a detailed schedule identifying key milestones and a breakdown of the tasks by project partner. Make sure that your schedule takes into account the remaining homework assignments and your other course obligations (e.g., midterms).

You must have thought about the design at the high level and partitioning of work between you and your partner. The plan you come up will be your master plan for the semester and you will be asked to update/revise the plan as we go along.

In addition to the design, you are expected to develop a detailed test plan, including high-level descriptions of component, module, and system tests. Include both project members names, email addresses, and team name on the report.

Look through the course calendar for the design-review, demo-1, demo-2, cache-demo, and final-demo dates and plan your work accordingly. These dates are non-negotiable and you must adhere to them. There will be a signup for a 15 minute meeting for design-review. Depending on how things shape up, we may do a signup and meetings for demo-1, demo-2, cache-demo and final-demo also.
Bring this report (printed) to class on the due date.

@srajmohan

Demo #2.0 - Pipelined design with Perfect Memory (30% of project grade)

http://pages.cs.wisc.edu/~karu/courses/cs552/spring2017/wiki/index.php/Main/ProjectDeadlinesAndGrading

Design review: (4% of project grade)

Each group needs to create a complete hand-drawn (or drawn with the aid of a graphing program like Openoffice draw) schematic of an unpipelined WISC-SP13 implementation. Each module, bus, and signal should be uniquely labeled. The schematic should be hierarchical so that the top level design contains only empty shells for each planned submodule. In general, there will be a one-to-one mapping of modules in your schematic to the modules you will eventually write in Verilog.

While explicitly drawing pipeline stages in the schematic is not required, you should still design with a pipeline in mind. It is a good idea to place modules near their final location in the pipelined design.
During the review, individual team members should be able to describe the datapath of any legal WISC-SP13 instruction using the schematic as a reference. Teams will also be expected to defend the design decisions that they make. You need to have thought through the control path and decode logic. Not necessary to have done a complete table of signals, but if you have such a table with the control signal values for every instruction, that would be great.

Signup instructions are posted. You should sign-up for a time-slot in the google doc. Write each partner's last name against a time-slot. If none works, discuss with your class mates about a possible swap. If you still cannot find a time-slot that works, email both the TAs and Karu.

Both partners are required to be present and both are expected to explain and answer questions about the whole design. Answering a question with: "I have no idea, my partner did that" is a failing answer. You must (at least) be able to answer: "My partner implemented that, but it works in the following way....".