DMA access problem

[Qw1chen]

DMA access problem

[axdy]

Hi there,

Apologies for the delayed reply.

Could you elaborate why you need to remove the decimation and interpolation filters? Removing these and replacing them with an interconnect will not work and it will very likely crash the board since the dma's will no longer receive a tlast signal.

If you would like to change the clock rates of the design I would suggest editing the simulink models in boards/ip/sysgen and ensuring a simulation of your changes works before changing the Vivado block design.

Regards,
Andrew

[Qw1chen]

hi,
I removed interpolation and decimation to use the RF data converter bypass mode. I added a tlast signal, and now I can receive a signal. However, I'm encountering a discrepancy: the amplitude of the real part received in the ADC is different from that of the imaginary part. Do you know the reason for this?
the weird result is below:


Thank you!

[axdy]

Hi there,

This is likely due to the phase offset incurred during transmission and reception. You can adjust the transmitting and receiving the phase offset by altering the MixerSettings['PhaseOffset'] variable for either the adc_block or dac_block.

Hope that helps,
Andrew

[Qw1chen]

Can I ask why the phase offset between the dac and adc causes amplitude degradation?
So if I perform phase calibration, can I avoid this effect?

Thank you very much!
This helps a lot!