strath-sdr/rfsoc_qpsk

PYNQ example of using the RFSoC as a QPSK transceiver.

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RFSoC QPSK Transceiver

This repository is only compatible with PYNQ images v2.7 and greater for the following RFSoC development boards:

• ZCU208,
• ZCU216,
• ZCU111,
• RFSoC4x2,
• RFSoC2x2.

Introduction

This repo contains all the files needed to build and run the RFSoC QPSK demonstrator that was published in IEEE Access and was presented at both FPL and XDF conferences in 2018. The design is a full QPSK transceiver, which transmits and receives randomly-generated pulse-shaped symbols with full carrier and timing synchronisation. PYNQ is used to visualise the data at both the DAC and ADC side of the RFSoC data converters, as well as visualising various DSP stages throughout the transmit and receive signal path.

Quick Start

Follow the instructions below to install the QPSK demonstrator on your development board. You will need to give your board access to the internet.

• Power on your RFSoC development board with an SD Card containing a fresh PYNQ v2.7 image or greater.
• Navigate to Jupyter Labs by opening a browser (preferably Chrome) and connecting to http://<board_ip_address>:9090/lab.
• We need to open a terminal in Jupyter Lab. Firstly, open a launcher window as shown in the figure below:

• Now open a terminal in Jupyter as illustrated below:

• Now simply install the QPSK demonstrator through PIP by executing the following command in the terminal:

pip3 install https://github.com/strath-sdr/rfsoc_qpsk/releases/download/v1.4.5/rfsoc_qpsk.tar.gz
python -m rfsoc_qpsk install

Once installation has complete, you will find the QPSK demonstrator notebooks located in the jupyter home workspace in the rfsoc_qpsk folder.

This repository uses Voila to create simple web applications using Jupyter notebooks. Your RFSoC development board should already be preinstalled with a version of Voila and no further setup is required.

Using the Project Files

The following software is required to use the project files in this repository.

• Vivado Design Suite 2020.2
• System Generator for DSP
• MATLAB R2020a

System Generator

The Tx and Rx IPs are in separate directories in rfsoc_qpsk/boards/ip/sysgen/ that can be opened using the appropriate System Generator dialogue. Due to the large amount of decimation and interpolation in both IPs, simulating the output can take an extraordinarily long time. A less extreme multirate system would simulate much faster!

Vivado

This project can be built with Vivado from the command line. Open Vivado 2020.2 and execute the following into the tcl console:

cd /<repository-location>/boards/<board-name>/rfsoc_qpsk/

Now that we have moved into the correct directory, make the Vivado project by running the make commands below sequentially.

make block_design
make bitstream

Alternatively, you can run the entire project build by executing the following into the tcl console:

make all

License

BSD 3-Clause

rfsoc_qpsk's Issues

DMA access problem

I'm reimplementing the QPSK transceiver and need to change the DAC and ADC clock values. I've removed the interpolate and decimate modules and replaced them with an AXI interconnect. However, now when I try to access the DMA using tx_ch0 = ol.qpsk_tx.axi_dma_0.sendchannel, the board crashes. I've been stuck on this issue for several days and can't figure out what the problem is. Can you help?

If you need design to figure out the problem, the link is:
https://drive.google.com/file/d/1_F2dnBlpuOJDBUTIe2o9Da3YWPtihrWC/view?usp=sharing
Thank you very much!

Simulink model QPSK Receiver

Hello!
Full simulink model of QPSK receiver available?
AXI QPSK Receiver: Coarse Frequency Sync simulink model not simulate.

Ubuntu 16.04 write_project.tcl seg fault

Hello, I have tried twice to run the build_project.tcl script as specified in the readme and both times my os has killed the process. I attached a file containing the end of the build process output, my computer memory, and os version. Is there another way I can build the project on my system or access the vivado block diagram without building it myself? P.S. I was able to successfully build the project from April 5th.
error.log

SysGen and iprepo HDL out of sync

Fix in PR#1 (#1) has been applied to generated HDL only.

Can someone with SysGen access update the data inspector for the last rx "tap off"? FIFO depth should be 127, and the constant for the read threshold should be 63.

Error in reading bit file in qpsk overlay

Hi All;
I try to reimplement the design through generating the file from system generator, then exporting the bit file from Vivado 2020.1. I've generated the bit file successfully and include it within the same path included in pynq image. However when I try to read it from the QPSK overlay this error appear . If I use the original file it works. Do I missed any permission request during bit file generation?

Symbol Timing Synchronisation

This issue concerns the system generator model named axi_qpsk_rx_tsync.slx.

The timing synchronization mask implements the PLL filter coefficients in accordance with equations (7.30) and (7.31) on pages 267 and 268 in [1].

The first coefficient is generated correctly, however, the second is off slightly due to a missing bracket in the "Timing Sync" block mask.

Currently used code: Kb = (4*(BnS*Ts)^2)/(Kn*Ks*(d+1/4*d)^2);

Corrected code: Kb = (4*(BnS*Ts)^2)/(Kn*Ks*(d+1/(4*d))^2);

This leads to a very small gain error that may lead to desynchronization problems. Further analysis and testing are required to check timing synchronization with corrected gains.

[1] — R. W. Stewart, K. Barlee, D. S. W. Atkinson, and L. H. Crockett, Software Defined Radio using MATLAB & Simulink and the RTL-SDR, Published by Strathclyde Academic Media, 2015.

AttributeError and Javascript Error

Hi There,
Unfortunately when I try to use jupyterlab or jupyter notebook I get the following error

AttributeError: module 'plotly.graph_objs' has no attribute 'FigureWidget'

When I try to use jupyterlab I get the additional error
Javascript Error: require is not defined

I installed the packages as per https://github.com/strath-sdr/rfsoc_qpsk

pip3 install --upgrade git+https://github.com/strath-sdr/rfsoc_qpsk.git

jupyter labextension install @jupyter-widgets/[email protected] --no-build
jupyter labextension install [email protected] --no-build
jupyter labextension install @jupyterlab/[email protected] --no-build
jupyter lab build

systemctl restart jupyter

I think there is a package compatibility issue with the install. My installed packages are
root@pynq:/home/xilinx# pip3 list
DEPRECATION: The default format will switch to columns in the future. You can use --format=(legacy|columns) (or define a format=(legacy|columns) inyour pip.conf under the [list] section) to disable this warning.
2ping (4.1)
alabaster (0.7.8)
asn1crypto (0.24.0)
attrs (17.4.0)
Babel (2.4.0)
beautifulsoup4 (4.6.0)
bleach (2.1.2)
certifi (2019.6.16)
cffi (1.11.5)
chardet (3.0.4)
Click (7.0)
cryptography (2.1.4)
cycler (0.10.0)
Cython (0.26.1)
dash (0.21.1)
dash-core-components (0.23.0)
dash-html-components (0.11.0)
dash-renderer (0.13.0)
decorator (4.4.0)
deltasigma (0.2.2)
docutils (0.14)
entrypoints (0.2.3.post1)
Flask (1.0.3)
Flask-Compress (1.4.0)
html5lib (0.999999999)
httplib2 (0.9.2)
idna (2.8)
imagesize (0.7.1)
imutils (0.5.2)
ipykernel (4.8.2)
ipython (5.5.0)
ipython-genutils (0.2.0)
ipywidgets (6.0.0)
itsdangerous (1.1.0)
Jinja2 (2.10)
jsonschema (2.6.0)
jupyter-client (5.2.2)
jupyter-contrib-core (0.3.3)
jupyter-contrib-nbextensions (0.5.1)
jupyter-core (4.4.0)
jupyter-highlight-selected-word (0.2.0)
jupyter-latex-envs (1.4.6)
jupyter-nbextensions-configurator (0.4.1)
jupyterlab (0.35.6)
jupyterlab-server (0.2.0)
keyring (10.6.0)
keyrings.alt (3.0)
lxml (4.2.1)
MarkupSafe (1.0)
matplotlib (2.1.1)
mistune (0.8.3)
mpmath (1.0.0)
nbconvert (5.3.1)
nbformat (4.4.0)
nbsphinx (0.3.1)
nbwavedrom (0.2.0)
netifaces (0.10.4)
networkx (1.11)
nose (1.3.7)
notebook (5.2.2)
numexpr (2.6.4)
numpy (1.13.3)
olefile (0.45.1)
pandas (0.22.0)
pandocfilters (1.4.2)
pexpect (4.2.1)
pickleshare (0.7.4)
Pillow (5.1.0)
pip (9.0.1)
plotly (3.9.0)
pluggy (0.6.0)
ply (3.11)
prompt-toolkit (1.0.15)
psutil (5.4.2)
py (1.5.2)
pycparser (2.18)
pycrypto (2.6.1)
pycurl (7.43.0.1)
pyeda (0.28.0)
Pygments (2.2.0)
pygobject (3.26.1)
pygraphviz (1.4rc1)
pynq (2.4)
pyparsing (2.2.0)
pytest (3.3.2)
pytest-sourceorder (0.5)
python-apt (1.6.0)
python-dateutil (2.6.1)
pytz (2019.1)
PyWavelets (0.5.1)
pyxdg (0.25)
PyYAML (3.12)
pyzmq (16.0.2)
requests (2.22.0)
requests-unixsocket (0.1.5)
retrying (1.3.3)
rfsoc-qpsk (1.0)
rise (5.2.0)
roman (2.0.0)
scikit-image (0.13.1)
scipy (0.19.1)
SecretStorage (2.3.1)
setuptools (39.0.1)
simplegeneric (0.8.1)
six (1.12.0)
Sphinx (1.6.7)
sphinx-rtd-theme (0.4.3)
SQLAlchemy (1.1.11)
ssh-import-id (5.7)
sympy (1.1.1)
systemd-python (234)
tables (3.4.2)
terminado (0.7)
testpath (0.3.1)
tornado (4.5.3)
traitlets (4.3.2)
transitions (0.5.3)
unattended-upgrades (0.1)
urllib3 (1.25.3)
uvloop (0.8.1)
wcwidth (0.1.7)
webencodings (0.5)
Werkzeug (0.15.4)
wheel (0.30.0)
widgetsnbextension (2.0.1)
xrfclk (0.1)
xrfdc (0.1)
root@pynq:/home/xilinx#

Therefore I would be grateful if someone would advise me if they have seen this issue and if there are any fixes available please provide the details.

Regards

Walter

Error in reading bitstream file and hwh file in qpsk overlay

I used the commands make block_design and make bitstream to generate the .bit and .hwh files for the ZCU216 board. The files were successfully generated and are located at:

.bit file: block_design.runs/impl_1/rfsoc_qpsk_wrapper.bit
.hwh file: block_design.gen/sources_1/bd/rfsoc_qpsk/hw_handoff/rfsoc_qpsk.hwh
I uploaded these files to a Jupyter notebook and followed the instructions in the 02_rfsoc_qpsk_demonstrator.ipynb notebook. However, after executing the command ol = QpskOverlay(), the Jupyter notebook shut down and I lost connection to the Jupyter Lab over Ethernet.

Could you help identify any missing steps or errors in the process before loading the bitstream onto the board?

Can I send a custom message to the QPSK transmitter?

Hello, I'm working on the ZCU111 to build a QPSK transmitter.
I can't figure out how to send a custom message use the pynq to the hardware to do the QPSK modulation.
I also use the TCL console to create the project. But I find that there is no constraints file in the project.

One error occurs when running the notebook

why the rf data converter needs two dac tile?

as tilte, I'm curious about why it needs two dac tile but only transmitted only one dac block data.

.dcp file

We are working through the qpsk_tx_symbol_gen_bd.xpr and the issue stalls at DCP does not exist.

Could be related to synthesis configuration issues, but would like to see if you could share the .dcp file?

Error using Voila notebook

Hello. I installed voila as you mention https://strath-sdr.github.io/pynq/linux/zynq/fpga/voila/2021/02/22/install-voila-on-pynq-v2-6.html.
After i run in a command line:

voila /home/xilinx/jupyter_notebooks/qpsk-demonstrator/voila_rfsoc_qpsk_demonstrator.ipynb --ExecutePreprocessor.timeout=180 --theme=dark --port=8866 --TagRemovePreprocessor.remove_cell_tags='{"ignore_me"}'

Then open new browser tab and enter the following into the address bar: http://board_ip_address:8866 but i get:

Vivado 19.2 Upgrade IP issues

Do you folks know what the comparable upgrade to would be from 18.3 to 19.2:
'axi_qpsk_rx_csync_bd_axi_qpsk_rx_csync_1_0'
'axi_qpsk_rx_dec_bd_axi_qpsk_rx_dec_1_0'
axi_qpsk_rx_rrc_bd_axi_qpsk_rx_rrc_1_0'
'axi_qpsk_rx_tsync_bd_axi_qpsk_rx_tsync_1_0'
'qpsk_tx_symbol_gen_bd_qpsk_tx_symbol_gen_1_0'
'axi_qpsk_rx_csync_0'
'axi_qpsk_rx_dec_0'
'axi_qpsk_rx_rrc_0'
'axi_qpsk_rx_tsync_0'
'qpsk_tx_symbol_gen_0'

Or definitions of the clock, sync settings would help to move this to 19.2.

How to change QPSK data rate to 10kbps?

Hi,
I'm trying to change the QPSK symbol rate to 10kbps.
I just change Rb = 10000(from 1000) and R_CIC = 320(from 3200).
After that, I build the Tx/Rx IPs and the bitstream file.
But, observing the RF output of qpsk_tx, the signal BW still seems about 1kHz.
Could you tell me what other configurations to be changed?

The constraints files of ZCU111 is empty

The "constraints.xdc" under "rfsoc_qpsk/boards/ZCU111/rfsoc_qpsk/" is an empty file.

Add the ZCU670 Development Board

With or without the CLK104 board.

Error when running the notebook

Ran the following lines in Jupyter Lab on a v2.4 PYNQ image for zcu111:

pip3 install --upgrade git+https://github.com/strath-sdr/rfsoc_qpsk.git

jupyter labextension install @jupyter-widgets/[email protected]
jupyter labextension install [email protected]
jupyter labextension install @jupyterlab/[email protected]

Then when running the notebook i get the following errors:

I suspect it has to do with warnings I received during the labextension installations:

Can you assist?