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This project forked from eugene-tarassov/vivado-risc-v

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Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Shell 0.08% C++ 0.01% Python 0.09% C 38.61% Java 18.83% Scala 0.45% Tcl 37.11% VHDL 0.41% Verilog 3.30% Assembly 0.02% ANTLR 0.77% Makefile 0.33%

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