Peeking zero-width I/Os

[ucb-bar]

Peeking zero-width I/Os

[edwardcwang]

[chick]

Hmm. This would be easy to do, perhaps as a mode where you can poke or peek anything you want without erroring. But treadle only has symbols for things that have survived all the way to low firrtl. so it would not otherwise know that the signal is zero length, it just simply isn't there, right?

[edwardcwang]

Yeah, that's the tricky part methinks... Zero-width signals do indeed disappear in low-FIRRTL. I guess this is the inverse of #2.

[ducky64]

Perhaps zero-width signals shouldn't disappear in low-FIRRTL? Even in Chisel frontend we kind of have a distinction between zero-width signals and optional Bundle fields, and zero width signals could be considered to be a form of design intent?

[edwardcwang]

Well, zero-width wires are also a Chisel/Chirrtl thing and don't actually exist in hardware...

[chick]

Annotations

[ekiwi]

This should be fixed by: 7d98ab5