Comments (3)
An uninitialized register should essentially be able to emulate the behavior of anyconst
.:
val myConst = Reg(UInt(8.W))
Registers without a reset value will start at an arbitrary constant (solver chosen in case of formal) and then, assuming you do not assign anything to them, they will retain their value.
from chiseltest.
Would the following have the same effect?
assume(stable(input))
from chiseltest.
Would the following have the same effect?
I think so. The only downside here is that to make an input you need to be in the top-level module. Registers can easily declared independent of module hierarchy.
from chiseltest.
Related Issues (20)
- Checking formal properties over multiple tests HOT 2
- Proving formal properties HOT 4
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- Report assert message with `FailedBoundedCheckException` HOT 1
- Generate waveform file in real-time HOT 1
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- assertion failed: The Chisel compiler plugin is now required for compiling Chisel code HOT 1
- The waveform doesn't reflect changes in the input port until io.clock.peek HOT 1
- scala.NotImplementedError: TODO: convert DecodeTableAnnotatio HOT 7
- Will there be a chiseltest 6.0.0? HOT 16
- Frequent crash on macOS with the threaded Verilator backend HOT 6
- AXI4RAM test failed on chiseltest 5.0.2 HOT 2
- Cant ```import chiseltest._``` HOT 1
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from chiseltest.