Comments (4)
I also had in mind to create something that will be simulator independent and working with both chiseltest and chiselsim.
Honestly, I would just pick one. Think of your thesis as creating a prototype that demonstrates a concept. Otherwise you will get bogged down in too many engineering-y things that won't matter in the end. Feel free to send an email to my @berkeley.edu email if you want to have a chat about your project. It sounds quite interesting and I might have a lot of knowledge that could help you get started.
from chiseltest.
It says that ChiselTest is not longer supported for new chisel features.
Well, to clarify: chiseltest
no longer gets first-class support from the Chisel core team, meaning that when they add features to Chisel, they won't spend time adding support for them to chiseltest
. If people in the community want to try and add support for new Chisel features to chiseltest
I would be happy to review your PRs.
The unfortunate reality though is that everyone contributing to chiseltest
is doing so unpaid and in their free time, whereas the Chisel core team has almost 10 engineers paid by SiFive. So keeping up with them adding features to Chisel will be a loosing battle. However, if your circuits do not use these new features, then they should still work with chiseltest
. Many of the new features in Chisel 6 don't really make sense with chiseltest
anyways. Probes and layers are mostly targeting designers that want to verify the resulting SystemVerilog with their own UVM style testbenches. This is important for SiFives business, but not necessarily for open-source designs.
So, what are the future developments for chiseltest?
Whatever the community wants to do. For now, chiseltest has more features like formal verification and multi-threaded testbenches, but new Chisel features aren't yet supported and we are lacking behind on releases (there hasn't been a stable 6.0 release of chiseltest yet).
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@rameloni : I saw your issue on whether GTKWave supports plugins. You might want to look into Surfer instead: https://gitlab.com/surfer-project/surfer
The code base is much newer and easier to extend. It already has special support for displaying Spade types (Spade is a new hardware language from the same author as Surfer) and I am sure they would be open to adding support for displaying Chisel and maybe also Tydi types.
from chiseltest.
@rameloni : I saw your issue on whether GTKWave supports plugins. You might want to look into Surfer instead: https://gitlab.com/surfer-project/surfer
The code base is much newer and easier to extend. It already has special support for displaying Spade types (Spade is a new hardware language from the same author as Surfer) and I am sure they would be open to adding support for displaying Chisel and maybe also Tydi types.
@ekiwi thank you! I will take a look into that, and probably I will ask for opinions from the creator of surfers.
If you read the issue on gtkwave you'll probably know what my project consists of.
I'm starting now with the actual implementation for the project and the waveform visualisation is something that will come later (I guess in a month). I first need to map and elaborate chisel structures to map them to simulation values.
I also had in mind to create something that will be simulator independent and working with both chiseltest and chiselsim.
from chiseltest.
Related Issues (20)
- JRE detects `EXCEPTION_ACCESS_VIOLATION` when trying to use Verilator as Chiseltest's backend HOT 2
- Report assert message with `FailedBoundedCheckException` HOT 1
- Generate waveform file in real-time HOT 1
- chiseltest gets the signal name wrong when trying to peek, poke, or expect an OpaqueType HOT 3
- Solver Chosen Constants for Formal Verification HOT 3
- scala.NotImplementedError: TODO: convert ThrowOnFirstErrorAnnotation HOT 3
- Bundle literal construction outside test() is not allowed in Chiseltest 5.0.0 (works in 0.5.4) HOT 2
- assertion failed: The Chisel compiler plugin is now required for compiling Chisel code HOT 1
- The waveform doesn't reflect changes in the input port until io.clock.peek HOT 1
- scala.NotImplementedError: TODO: convert DecodeTableAnnotatio HOT 7
- Will there be a chiseltest 6.0.0? HOT 16
- Frequent crash on macOS with the threaded Verilator backend HOT 6
- AXI4RAM test failed on chiseltest 5.0.2 HOT 2
- Cant ```import chiseltest._``` HOT 1
- Bitwuzla has changed it's command line argument format HOT 1
- [WARNING] Unsupported annotation: SRAMAnnotation
- [Help]A TLRAM test failed log HOT 8
- Who is the copyright holder of chiseltest and what is the license? HOT 1
- one step takes extremely long time to complete HOT 2
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from chiseltest.