ultraembedded/core_usb_fs_phy

USB Full Speed PHY

core_usb_fs_phy's Issues

Latch inferred for signal `\usb_transceiver.\out_dp'

Latches are inferred for out_dp and out_dn at:
https://github.com/ultraembedded/core_usb_fs_phy/blob/master/src_v/usb_transceiver.v#L101

What is the proper way to rewrite it to remove the latch ?

Would following change be ok ?

diff --git a/src_v/usb_transceiver.v b/src_v/usb_transceiver.v
index 53b6a63..9d81abf 100644
--- a/src_v/usb_transceiver.v
+++ b/src_v/usb_transceiver.v
@@ -121,14 +121,14 @@ begin : MUX
             out_dp = 1'b1;
             out_dn = 1'b0;
         end
-        else if (usb_phy_tx_dp_i == 1'b1 && usb_phy_tx_dn_i == 1'b1)
+        else
         begin
             // SE0 (both low)
             out_dp = 1'b0;
             out_dn = 1'b0;
         end
     end
-    1'b1 :
+    default :
     begin
         if (usb_phy_tx_dp_i == 1'b0 && usb_phy_tx_dn_i == 1'b0)
         begin
@@ -148,7 +148,7 @@ begin : MUX
             out_dp = 1'b1;
             out_dn = 1'b0;
         end
-        else if (usb_phy_tx_dp_i == 1'b1 && usb_phy_tx_dn_i == 1'b1)
+        else
         begin
             // Illegal
             out_dp = 1'b1;