Giter Site home page Giter Site logo

vardhansuroshi / vlsi-asic-design-flow Goto Github PK

View Code? Open in Web Editor NEW
2.0 1.0 0.0 3 MB

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

Shell 0.17% C 0.06% SystemVerilog 0.01% Assembly 0.03% Verilog 99.73%
openlane opensource risc-v rtl vlsi vlsi-design vlsi-physical-design asic-design skywater

vlsi-asic-design-flow's Introduction

Typing SVG

💫 About Me:

Coding

Hey there! I'm Vardhan, the final-year B.Tech ninja at PES University.



You can find me buried under a pile of paper & books📚, sipping tea🍵, and occasionally questioning❓my life choices.

I work with cool folks at CHIPS on making chips💻 that don't just snack on energy but also do a mean moonwalk in efficiency. Think of it as my way of making circuits eco-friendly♻️.

I'm that guy who finds joy in VLSI and thinks digital design is cooler than a <some_adjective>!! I'm basically a digital design enthusiast, turning 1s and 0s into magic spells

You can Reach me at:

www.linkedin.com/in/vardhansuroshi

💻 Tools I wield like a wizard:

arduino    sv    sv    c    linux    matlab    python    openroad    cadence   

Check out my projects:

  • Ever wanted to dive deep into the magical world of VLSI design? Well, you're in luck! This repository is dedicated to VLSI ASIC Design Flow using open-source tools!
  • Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
  • This project offers an immersive tutorial experienced within the context of the Advanced Physical Design. This repo is the continuity of VLSI ASIC Design Flow.
  • Armed with nothing but my trusty keyboard and a lot of tea. In this adventure, we'll explore the Opensource ASIC Design tool OpenLANE and emerge victorious!
  • This project involves the designing of a 4X4 (16-bit) SRAM Memory Array and peripheral logics using Cadence Virtuoso.
  • It's like playing with LEGOs, but way cooler😎 and with a lot more frustration!

4. प्रयास (Prayaas)

  • प्रयास is a 32-bit RISC-V I-type processor! {Work in progress } Currently on a ride designing, writing coding, debugging, and reaching existential crises.
  • Will it work? Who knows! But hey, it's the journey that counts, right?

Also do check out my, "not so cool" projects here

📊 GitHub Stats:

vlsi-asic-design-flow's People

Contributors

vardhansuroshi avatar

Stargazers

 avatar

Watchers

 avatar

Recommend Projects

  • React photo React

    A declarative, efficient, and flexible JavaScript library for building user interfaces.

  • Vue.js photo Vue.js

    🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.

  • Typescript photo Typescript

    TypeScript is a superset of JavaScript that compiles to clean JavaScript output.

  • TensorFlow photo TensorFlow

    An Open Source Machine Learning Framework for Everyone

  • Django photo Django

    The Web framework for perfectionists with deadlines.

  • D3 photo D3

    Bring data to life with SVG, Canvas and HTML. 📊📈🎉

Recommend Topics

  • javascript

    JavaScript (JS) is a lightweight interpreted programming language with first-class functions.

  • web

    Some thing interesting about web. New door for the world.

  • server

    A server is a program made to process requests and deliver data to clients.

  • Machine learning

    Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.

  • Game

    Some thing interesting about game, make everyone happy.

Recommend Org

  • Facebook photo Facebook

    We are working to build community through open source technology. NB: members must have two-factor auth.

  • Microsoft photo Microsoft

    Open source projects and samples from Microsoft.

  • Google photo Google

    Google ❤️ Open Source for everyone.

  • D3 photo D3

    Data-Driven Documents codes.