westerndigitalcorporation/swerv-iss

Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator

swerv-iss's Issues

Default c++ build flag -mfma causing Illegal Instruction error

This flag makes the compiler generate code that takes advantage of the UltraSPARC Fused Multiply-Add Floating-point instructions.

This causes cryptic 'Illegal Instruction' errors on CPU's that don't support this (which has proved to be plentiful). Can this not be made default, please?

Thanks.

Query regarding usage of GDB command line option

Hello,

I have a query regarding the command line option: --gdb.
How do I use the option to enable remote GDB session?

Currently I have observed the GDB output on stdout.
I have written a script which redirect the whisper simulator stdout and stdin through netcat.

But it is an inelegant solution since, I lose any stdout prints from riscv binaries linked with newlib.

Thank you for the assistance.
-Ameya Vikram Singh

Query regarding usage of ISS in Virtual Platforms(VP)

Hello,

I have following queries regarding the swerv-ISS:

• Is there a SoC Virtual Platform developed using this ISS?
• Is there some provision to integrate this ISS with HDL simulation environments (SystemC, Verilog etc..)?

Regards,
Ameya Vikram Singh

Memory.cpp:583:54: error: cannot convert 'gzFile_s**' to 'gzFile {aka gzFile_s*}'

It appears that whisper needs a specific zlib version to compile. Running under ubuntu 18.04 or 19.10, with the default zlib installation, gives the following compilation failures:

Memory.cpp: In member function 'bool WdRiscv::Memory::saveSnapshot(const string&)':
Memory.cpp:583:54: error: cannot convert 'gzFile_s**' to 'gzFile {aka gzFile_s*}' for argument '1' to 'int gzwrite(gzFile, voidpc, unsigned int)'
       int resp = gzwrite(gzout, buffer, current_chunk);
                                                      ^
Memory.cpp:594:16: error: cannot convert 'gzFile_s**' to 'gzFile {aka gzFile_s*}' for argument '1' to 'int gzclose(gzFile)'
   gzclose(gzout);
                ^
Memory.cpp: In member function 'bool WdRiscv::Memory::loadSnapshot(const string&)':
Memory.cpp:608:29: error: cannot convert 'gzFile_s**' to 'gzFile {aka gzFile_s*}' for argument '1' to 'int gzeof(gzFile)'
   if (not gzin or gzeof(gzin))
                             ^
Memory.cpp:624:52: error: cannot convert 'gzFile_s**' to 'gzFile {aka gzFile_s*}' for argument '1' to 'int gzread(gzFile, voidp, unsigned int)'
       int resp = gzread(gzin, buffer, current_chunk);
                                                    ^
Memory.cpp:627:31: error: cannot convert 'gzFile_s**' to 'gzFile {aka gzFile_s*}' for argument '1' to 'int gzeof(gzFile)'
           success = gzeof(gzin);
                               ^
Memory.cpp:636:54: error: cannot convert 'gzFile_s**' to 'gzFile {aka gzFile_s*}' for argument '1' to 'const char* gzerror(gzFile, int*)'
               << " failed: " << gzerror(gzin, nullptr) << "\n";
                                                      ^
Memory.cpp:639:26: error: cannot convert 'gzFile_s**' to 'gzFile {aka gzFile_s*}' for argument '1' to 'int gzeof(gzFile)'
   else if (not gzeof(gzin))
                          ^
Memory.cpp:642:15: error: cannot convert 'gzFile_s**' to 'gzFile {aka gzFile_s*}' for argument '1' to 'int gzclose(gzFile)'
   gzclose(gzin);

Modifying the code as follows works:

@@ -563,7 +563,7 @@ Memory::saveSnapshot(const std::string & filename)

-  gzFile* gzout = (gzFile*) gzopen(filename.c_str(), "wb");

+  gzFile gzout = (gzFile) gzopen(filename.c_str(), "wb");


@@ -604,7 +604,7 @@ Memory::loadSnapshot(const std::string & filename)

-  gzFile * gzin = (gzFile *)gzopen(filename.c_str(), "rb");

+  gzFile gzin = (gzFile)gzopen(filename.c_str(), "rb");```

Running in lockstep with Verilog simulator

"It can also run in lock step with a Verilog simulator serving as a "golden model" against which an implementation is checked after each instruction of a test program."

Do you have documentation how use your ISS "in lock step" with Modelsim/Questasim? I have one open source design I'm creating (www.hdlexpress.com see RisKy1) that I'd like to try and use your ISS with. I'm at a point where I can compile C & assembly code and run the code in my System Verilog simulations of my RTL design.

Turning on --log changes instruction count

I'm running test2.c from the README. When I add --log for an instruction trace, the count of retired instructions increases by 1.

I can't imagine any good reason why turning on tracing should change the number of retired instructions. It should be running the exact same thing in either case.

sjohnson@tyrone:/d1/proj/sjohnson/swerv-ISS$ ./whisper test2
Successful stop: write to to-host
Retired 27 instructions in 0.00s  177631 inst/s
sjohnson@tyrone:/d1/proj/sjohnson/swerv-ISS$ ./whisper --log test2
#1 0 000100a8     1141 r 02         fffffff0  c.addi   x2, -0x10
#2 0 000100aa     c606 m fffffffc   00000000  c.swsp   x1, 0xc
#3 0 000100ac     c422 m fffffff8   00000000  c.swsp   x8, 0x8
#4 0 000100ae     0800 r 08         00000000  c.addi4spn x8, 0x4
#5 0 000100b0     4581 r 0b         00000000  c.li     x11, 0x0
#6 0 000100b2     4501 r 0a         00000000  c.li     x10, 0x0
#7 0 000100b4     37c1 r 01         000100b6  c.jal    . - 0x40
#8 0 00010074     7179 r 02         ffffffc0  c.addi16sp -0x3
#9 0 00010076     d622 m ffffffec   00000000  c.swsp   x8, 0x2c
#10 0 00010078     1800 r 08         fffffff0  c.addi4spn x8, 0xc
#11 0 0001007a fca42e23 m ffffffcc   00000000  sw       x10, -0x24(x8)
#12 0 0001007e fcb42c23 m ffffffc8   00000000  sw       x11, -0x28(x8)
#13 0 00010082     4785 r 0f         00000001  c.li     x15, 0x1
#14 0 00010084 fef42623 m ffffffdc   00000001  sw       x15, -0x14(x8)
#15 0 00010088     4789 r 0f         00000002  c.li     x15, 0x2
#16 0 0001008a fef42423 m ffffffd8   00000002  sw       x15, -0x18(x8)
#17 0 0001008e fec42703 r 0e         00000001  lw       x14, -0x14(x8)
#18 0 00010092 fe842783 r 0f         00000002  lw       x15, -0x18(x8)
#19 0 00010096     97ba r 0f         00000003  c.add    x15, x14
#20 0 00010098 fef42223 m ffffffd4   00000003  sw       x15, -0x1c(x8)
#21 0 0001009c fe442783 r 0f         00000003  lw       x15, -0x1c(x8)
#22 0 000100a0     853e r 0a         00000003  c.mv     x10, x15
#23 0 000100a2     5432 r 08         00000000  c.lwsp   x8, 0x2c
#24 0 000100a4     6145 r 02         fffffff0  c.addi16sp 0x3
#25 0 000100a6     8082 r 00         00000000  c.jr     x1
#26 0 000100b6     67c5 r 0f         00011000  c.lui    x15, 0x11
#27 0 000100b8     4705 r 0e         00000001  c.li     x14, 0x1
#28 0 000100ba 0ce7a423 m 000110c8   00000001  sw       x14, 0xc8(x15)
Successful stop: write to to-host
Retired 28 instructions in 0.00s  22047 inst/s
sjohnson@tyrone:/d1/proj/sjohnson/swerv-ISS$

Support for running on 32-bit systems

Hi,

I tried building it on a 32-bit Ubuntu machines with 1.67 boost libs and gcc 7.4

After fixing the initial errors in Core.cpp related to the usage of __uint128_t datatypes, I was able to compile it successfully on my system.

But when running the simple test as per the readme, I see the following errors:

rahul@rahul:~/work/swerv-ISS$ ./whisper build/test
Unreasonably small memory size (less than 0x 1000) -- using 0x1000
End of ELF segment 0 (100c8) is beyond end of simulated memory (1000)
End of ELF segment 1 (110c8) is beyond end of simulated memory (1000)
No loadable segment in ELF file
rahul@rahul:~/work/swerv-ISS$

On running the attached .hex file in the simulator, I see segmentation fault when enabling --log mode but without that option it seems to work well:

rahul@rahul:~/work/swerv-ISS$ ./whisper --hex inst_hex.hex --startpc 0x00000000 --maxinst 28
Unreasonably small memory size (less than 0x 1000) -- using 0x1000
Stopped -- Reached instruction limit
Retired 1c instructions in 0.00s  692b1 inst/s
rahul@rahul:~/work/swerv-ISS$ 

Using --log option:

rahul@rahul:~/work/swerv-ISS$ ./whisper --hex inst_hex.hex --startpc 0x00000000 --maxinst 28 --log
Unreasonably small memory size (less than 0x 1000) -- using 0x1000
Segmentation fault (core dumped)
rahul@rahul:~/work/swerv-ISS$ 

Any ideas on how to proceed ahead?

Compilation Failure due to optimizations on various compilers

Due to introduction of template method in Core/HartConfig class in this commit: 882de25#diff-fdf14d2fb8fede41af40647977544f4eR633

Compilation fails with undefined references of following methods:

bool WdRiscv::HartConfig::applyConfig<unsigned int>(WdRiscv::Hart<unsigned int>&, bool) const
bool WdRiscv::HartConfig::finalizeCsrConfig<unsigned int>(std::vector<WdRiscv::Hart<unsigned int>*, std::allocator<WdRiscv::Hart<unsigned int>*> >&) const
bool WdRiscv::HartConfig::applyMemoryConfig<unsigned int>(WdRiscv::Hart<unsigned int>&, bool) const
bool WdRiscv::HartConfig::applyConfig<unsigned long>(WdRiscv::Hart<unsigned long>&, bool) const
bool WdRiscv::HartConfig::finalizeCsrConfig<unsigned long>(std::vector<WdRiscv::Hart<unsigned long>*, std::allocator<WdRiscv::Hart<unsigned long>*> >&) const
bool WdRiscv::HartConfig::applyMemoryConfig<unsigned long>(WdRiscv::Hart<unsigned long>&, bool) const

The private static method in HartConfig class does not help alleviate this issue.
As compiler with varying optimization flag inline/removes the API's from the HartConfig.cpp.o object file.

The pull request #13 Fixes the issue.

missing includes

Hart.cpp is missing an
#include <atomic>

FpRegs.hpp is missing
#include <string>

which makes it fail to compile on my system
CentOS 7
gcc 10.2.0
boost 1.74.0 c++17

some problems which I find

Hello，I am a student. When I used it to test my use cases, the results were not consistent with my expectations.
the problem of my testcase is
#13923 0 00000000800002c8 800000b7 r 0000000000000001 ffffffff80000000 lui x1, -0x80000
#13924 0 00000000800002cc 8000bf13 r 000000000000001e 0000000000000000 sltiu x30, x1, 0x800
The value of reg x1 is 0xffffffff80000000, and the value of imm is 0x800. the imm should extend to 64-bits with sign, so the result should be 1,but the test is 0.

And I found lots of similar mistake cased of extending to 64-bits with sign.

I try to change the code of Hart.cpp. I changed the function of
“”“
template
void
Hart::execSltiu(const DecodedInst* di)
{
URV imm = di->op2();
URV v = intRegs_.read(di->op1()) < imm ? 1 : 0;
intRegs_.write(di->op0(), v);
}
“””
to
“””
template
void
Hart::execSltiu(const DecodedInst* di)
{
//URV imm = di->op2();
URV imm = SRV(int32_t(di->op2())); // Sign extend to 64-bits
URV v = intRegs_.read(di->op1()) < imm ? 1 : 0;
intRegs_.write(di->op0(), v);
}
“””
then ,I tested it .the problem is solved.

C++ Program either gets caught in infinite loop or get aborted!

I have a multi-file (3 .cpp files and 2 .h files) C++ code that uses new, new[], delete, and delete[] operators to allocate large chunks of memory and performs some floating point operations (requires division by sqrt()). The program compiles and runs well with regular g++ and produces the required output. I now want to convert it to RISC-V instructions.

1. I first used the GNU RISC-V compiler toolchain to compile the program with following command:
   riscv32-unknown-elf-g++ -w -march=rv32imafc -mabi=ilp32f -DPREALLOCATE=1 -mcmodel=medany -fno-common -static -Iinclude/ f1.cpp f2.cpp f3.cpp -o executable
   here executable is the compiled binary file.

2. Since no errors are thrown at compile time, I proceeded to run the whisper simulator as follows:
   whisper --isa imafc --target executable --logfile mylog --profileinst prfl
   where mylog and prfl are output file paths.

3. The log file generated exceeds 6 GB in size and it doesn't terminate, so I assume that it is stuck in some infinite loop.

4. I tried adding the _start() function and tohost variable which didn't work either (same problem as 3 above).

5. I generated an object dump for executable and captured the (hex) addresses of starting address of main(), its ending address and address of tohost and passed them as parameters to --startpc, --endpc and --tohost respectively, in which case, the program was aborted after 64 illegal operations and ~300 MB of log file.

I think I am making some mistake. Kindly help me fix this issue or share the correct steps to generate the RISC-V assembly instructions for my C++ program.

whisper --disass cli argument doesn't work

Hi there, I wanted a way to disassemble instructions to their symbolic names and as per the Readme, it is possible through the --disass param for whisper. However, it doesn't seem to be there.

Is this something which has been removed or yet to be implemented. If the general functionality is present but not exposed, I can try to implement it and submit a PR. Any pointers which can help me get started is appreciated.