wren6991/hazard3

3-stage RV32IMACZb* processor with debug

hazard3's Issues

Reversed address and data for SW command.

I'm using the cpu 1port. When I try to store word, it looks like it reverses the address and data.

The code is:
addi x1, x0, 4
addi x2, x0, 200
sw x1, 0(x2)

It trys to write to address 4 with data 200 instead of writing to address 200 with data 4. I'm not sure where they are getting swapped.

(Originally I was trying to write 2 to address 200, but I kept getting a misalignment error.)

what's the problem when I run 'make ' command ?

make failure

when we run 'make' command, here is the result:

make: listfiles: Command not found
make: listfiles: Command not found
mkdir -p build-tb.f
yosys -p 'read_verilog -I ../../../hdl -DCONFIG_HEADER="config_default.vh" ; hierarchy -top tb; write_cxxrtl build-tb.f/dut.cpp' 2>&1 > build-tb.f/cxxrtl.log
ERROR: Command syntax error: No filename given.
> read_verilog -I ../../../hdl -DCONFIG_HEADER="config_default.vh"
>                                                                  ^
make: *** [build-tb.f/dut.cpp] Error 1

Our environment is as following:

uname -a 
Linux bigdot-poweredge-R740 3.10.0-1160.95.1.el7.x86_64 #1 SMP Mon Jul 24 13:59:37 UTC 2023 x86_64 x86_64 x86_64 GNU/Linux

Help with JTAG DTM

I'm working on a bare bones JTAG in Python and using the Hazard3 as a test bench. (Once I get the TB going then I want to get an ECP5 going.) My JTAG code is here: https://github.com/tannewt/jtag To connect to the test bench do: python connect_to_remote.py 8298 with the tb run with ./tb --port 8298.

I'm trying to read a register via DMI and getting a 0x3 error back. I may just need to add more idle cycles. I've tried the 4 as the DTMCS register says and also 6. From our Twitter conversation it sounds like I should retry with more idle cycles. Is that right?

Here is a VCD: h3_jtag.zip

Nits: JTAGG -> JTAG

There is a minor spelling in the file: "JTAGG" should be "JTAG".

https://github.com/Wren6991/Hazard3/blob/e8b4578b4003d838f006dca00b5fea5852e4ab98/example_soc/fpga/fpga_ulx3s.f#L9C48-L9C53

error: Unable to place cell, cell type ICESTORM_LC

Errors for Icebreaker

Following the instructions for Building an example SOC for the iCEBreaker, I ran into this error:

ERROR: Unable to place cell 'soc_u.cpu.core.fast_branchcmp.branchcmp_u.op_a_SB_LUT4_O_20_LC', no BELs remaining to implement 

In more detail:

⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3 (master * u=) Wren6991/Hazard3

0 $  . sourceme
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3 (master * u=) Wren6991/Hazard3

0 $  cd example_soc/synth
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3

0 $  make -f Icebreaker.mk prog
>>> Synth

yosys -p "read_verilog -I../../hdl -DFPGA -DFPGA_ICE40 ../fpga/fpga_icebreaker.v ../libfpga/common/reset_sync.v ../libfpga/common/fpga_reset.v ../libfpga/common/activity_led.v ../libfpga/cdc/sync_1bit.v ../soc/example_soc.v ../../hdl/hazard3_core.v ../../hdl/hazard3_cpu_1port.v ../../hdl/hazard3_cpu_2port.v ../../hdl/arith/hazard3_alu.v ../../hdl/arith/hazard3_branchcmp.v ../../hdl/arith/hazard3_mul_fast.v ../../hdl/arith/hazard3_muldiv_seq.v ../../hdl/arith/hazard3_onehot_encode.v ../../hdl/arith/hazard3_onehot_priority.v ../../hdl/arith/hazard3_onehot_priority_dynamic.v ../../hdl/arith/hazard3_priority_encode.v ../../hdl/arith/hazard3_shift_barrel.v ../../hdl/hazard3_csr.v ../../hdl/hazard3_decode.v ../../hdl/hazard3_frontend.v ../../hdl/hazard3_instr_decompress.v ../../hdl/hazard3_pmp.v ../../hdl/hazard3_power_ctrl.v ../../hdl/hazard3_regfile_1w2r.v ../../hdl/hazard3_triggers.v ../../hdl/debug/dtm/hazard3_jtag_dtm.v ../../hdl/debug/dtm/hazard3_jtag_dtm_core.v ../../hdl/debug/cdc/hazard3_apb_async_bridge.v ../../hdl/debug/cdc/hazard3_reset_sync.v ../../hdl/debug/cdc/hazard3_sync_1bit.v ../../hdl/debug/dm/hazard3_dm.v ../libfpga/peris/uart/uart_mini.v ../libfpga/peris/uart/uart_regs.v ../libfpga/common/clkdiv_frac.v ../libfpga/common/sync_fifo.v ../libfpga/peris/spi_03h_xip/spi_03h_xip.v ../libfpga/peris/spi_03h_xip/spi_03h_xip_regs.v ../libfpga/mem/ahb_cache_readonly.v ../libfpga/mem/ahb_cache_writeback.v ../libfpga/mem/cache_mem_set_associative.v ../libfpga/mem/sram_sync.v ../libfpga/mem/ahb_sync_sram.v ../libfpga/busfabric/ahbl_crossbar.v ../libfpga/busfabric/ahbl_splitter.v ../libfpga/busfabric/ahbl_arbiter.v ../libfpga/common/onehot_mux.v ../libfpga/common/onehot_priority.v ../libfpga/busfabric/ahbl_to_apb.v ../libfpga/busfabric/apb_splitter.v; synth_ice40 -dsp; write_json fpga_icebreaker.json" > synth.log
tail -n 35 synth.log
51.53. Printing statistics.

=== fpga_icebreaker ===

   Number of wires:               7946
   Number of wire bits:          29330
   Number of public wires:        7946
   Number of public wire bits:   29330
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              14872
     SB_CARRY                      390
     SB_DFF                         75
     SB_DFFE                       113
     SB_DFFER                     4039
     SB_DFFES                       19
     SB_DFFESR                      32
     SB_DFFNR                        1
     SB_DFFR                        94
     SB_DFFS                         7
     SB_LUT4                     10094
     SB_RAM40_4K                     4
     SB_SPRAM256KA                   4

51.54. Executing CHECK pass (checking for obvious problems).
Checking module fpga_icebreaker...
Found and reported 0 problems.

52. Executing JSON backend.

Warnings: 26 unique messages, 40 total
End of script. Logfile hash: 7ff0402baf, CPU: user 85.47s system 1.12s, MEM: 968.21 MB peak
Yosys 0.20+70 (git sha1 6e907acf8, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 32% 14x proc_mux (31 sec), 15% 62x opt_expr (15 sec), ...
>>> Place and Route

nextpnr-ice40 -r --up5k --package sg48 --pcf fpga_icebreaker.pcf --json fpga_icebreaker.json --asc fpga_icebreaker.asc --timing-allow-fail --quiet --log pnr.log
ERROR: Unable to place cell 'soc_u.cpu.core.fast_branchcmp.branchcmp_u.op_a_SB_LUT4_O_20_LC', no BELs remaining to implement cell type 'ICESTORM_LC'
0 warnings, 1 error
make: *** [/mnt/c/workspace/hazard3/scripts/synth_ice40.mk:48: fpga_icebreaker.asc] Error 255

another attempt:

0 $  make -f Icebreaker.mk
>>> Place and Route

nextpnr-ice40 -r --up5k --package sg48 --pcf fpga_icebreaker.pcf --json fpga_icebreaker.json --asc fpga_icebreaker.asc --timing-allow-fail --quiet --log pnr.log
ERROR: Unable to place cell 'soc_u.cpu.core.fast_branchcmp.branchcmp_u.op_a_SB_LUT4_O_20_LC', no BELs remaining to implement cell type 'ICESTORM_LC'
0 warnings, 1 error
make: *** [/mnt/c/workspace/hazard3/scripts/synth_ice40.mk:48: fpga_icebreaker.asc] Error 255

Errors for ULX3S

The ULX3S also has an error:

0 $  make clean
rm -f fpga_icebreaker.json fpga_icebreaker.asc fpga_icebreaker.bin fpga_icebreaker_synth.v
rm -f synth.log pnr.log
rm -f pnr_try*.asc pnr*.log
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3

0 $  make -f ULX3S.mk
>>> Synth

yosys -p "read_verilog -I../../hdl -DFPGA -DFPGA_ECP5 ../fpga/fpga_ulx3s.v ../fpga/pll_25_50.v ../fpga/pll_25_40.v ../libfpga/common/reset_sync.v ../libfpga/common/fpga_reset.v ../soc/example_soc.v ../../hdl/hazard3_core.v ../../hdl/hazard3_cpu_1port.v ../../hdl/hazard3_cpu_2port.v ../../hdl/arith/hazard3_alu.v ../../hdl/arith/hazard3_branchcmp.v ../../hdl/arith/hazard3_mul_fast.v ../../hdl/arith/hazard3_muldiv_seq.v ../../hdl/arith/hazard3_onehot_encode.v ../../hdl/arith/hazard3_onehot_priority.v ../../hdl/arith/hazard3_onehot_priority_dynamic.v ../../hdl/arith/hazard3_priority_encode.v ../../hdl/arith/hazard3_shift_barrel.v ../../hdl/hazard3_csr.v ../../hdl/hazard3_decode.v ../../hdl/hazard3_frontend.v ../../hdl/hazard3_instr_decompress.v ../../hdl/hazard3_pmp.v ../../hdl/hazard3_power_ctrl.v ../../hdl/hazard3_regfile_1w2r.v ../../hdl/hazard3_triggers.v ../../hdl/debug/dtm/hazard3_jtag_dtm.v ../../hdl/debug/dtm/hazard3_jtag_dtm_core.v ../../hdl/debug/cdc/hazard3_apb_async_bridge.v ../../hdl/debug/cdc/hazard3_reset_sync.v ../../hdl/debug/cdc/hazard3_sync_1bit.v ../../hdl/debug/dm/hazard3_dm.v ../libfpga/peris/uart/uart_mini.v ../libfpga/peris/uart/uart_regs.v ../libfpga/common/clkdiv_frac.v ../libfpga/common/sync_fifo.v ../libfpga/cdc/sync_1bit.v ../libfpga/peris/spi_03h_xip/spi_03h_xip.v ../libfpga/peris/spi_03h_xip/spi_03h_xip_regs.v ../libfpga/mem/ahb_cache_readonly.v ../libfpga/mem/ahb_cache_writeback.v ../libfpga/mem/cache_mem_set_associative.v ../libfpga/mem/sram_sync.v ../libfpga/mem/ahb_sync_sram.v ../libfpga/busfabric/ahbl_crossbar.v ../libfpga/busfabric/ahbl_splitter.v ../libfpga/busfabric/ahbl_arbiter.v ../libfpga/common/onehot_mux.v ../libfpga/common/onehot_priority.v ../libfpga/busfabric/ahbl_to_apb.v ../libfpga/busfabric/apb_splitter.v ../../hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v; hierarchy -top fpga_ulx3s; synth_ecp5 -abc9 -json fpga_ulx3s.json" > synth.log
ERROR: Unterminated preprocessor conditional!
make: *** [/mnt/c/workspace/hazard3/scripts/synth_ecp5.mk:44: fpga_ulx3s.json] Error 1
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3

I can confirm synth_ecp5.mk:44 matches what I have locally $(YOSYS) -p "$(SYNTH_CMD)" > synth.log:

I have the latest toolchain installed, as of today, from:

https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2022-09-04/oss-cad-suite-linux-x64-20220904.tgz

Specifically there versions:

0 $  yosys --version
Yosys 0.20+70 (git sha1 6e907acf8, clang 10.0.0-4ubuntu1 -fPIC -Os)
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3

0 $  nextpnr-ice40 --version
nextpnr-ice40 -- Next Generation Place and Route (Version nextpnr-0.3-89-gf1349e11)
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3

0 $  which yosys
/mnt/c/download/yosyshq/oss-cad-suite/bin/yosys
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3

0 $  which nextpnr-ice40
/mnt/c/download/yosyshq/oss-cad-suite/bin/nextpnr-ice40
⦗OSS CAD Suite⦘ gojimmypi@DESKTOP(WSL): /mnt/c/workspace/hazard3/example_soc/synth (master * u=) Wren6991/Hazard3

If it helps, I have a blog with more details.

Any tips on what I might be doing wrong? Thanks.