xarklabs/upduino-example

Example UPduino project setup for Linux, macOS and WIndows+WSL for synthesis and simulation

upduino-example's Issues

make bin fails?

First of all, thanks for putting together this great example for UPDuino projects, I appreciate the effort you've put in to share it!

I've clone the project and was stepping through the README and got the tools setup properly (or so at least I assume at this point). And then I attempted a build via make bin, and the verilator lint fails by default with the following error:

$ make bin
=== Synthesizing design ===
verilator -sv --language 1800-2012 --trace-fst -I. -Werror-UNUSED -Wall -Wno-DECLFILENAME --lint-only -DNO_ICE40_DEFAULT_ASSIGNMENTS --top-module example_top /Users/justinwagner/tools/oss-cad-suite-build/darwin-arm64-20221124/share/yosys/ice40/cells_sim.v ./example_top.sv ./example_main.sv 2>&1 | tee logs/example_verilator.log
%Error-NEEDTIMINGOPT: example_top.sv:76:5: Use --timing or --no-timing to specify how delays should be handled
                                         : ... In instance example_top
   76 |     #(NS_48M)   clk = !clk;  
      |     ^
                      ... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=5.003
%Error: Exiting due to 1 error(s)
make: *** [out/example.json] Error 1

Is this intended, or did something change in newer versions of the OSS Cad Suite that is causing this?

I'm using this build: https://github.com/YosysHQ/oss-cad-suite-build/releases/tag/2022-11-24

Perhaps you were assuming an older version of these tools?