aklsh/hephaestus

8-Bit Processor

About

_{^{Generated with Platane/snk}}

My name is Akilesh Kannan. You'll usually find me on the internet as aklsh. My interests lie mostly in the hardware-software interface—low-level software (OS, networking), computer architecture and hardware accelerators. I am also huge supporter of GNU/Linux systems (haven't tried BSDs, so can't comment), Open-Source Software and Open Hardware.

Here's somethings that you can talk to me about:

1. Hardware. All kinds: Processors, Security, GPUs, Laptops, PC Builds etc.
2. TV Shows. Name any english TV show and I've probably watched it.
3. Music. Alternative, Rock, Electronic.
4. Ricing. I sometimes post my rices on r/unixporn.
5. Gaming. Console >> PC gaming. There's just something about a controller with a joystick.
6. Motorsport. I keep up with F1,2,3,E and am an avid fan of Scuderia Ferrari.

hephaestus's Issues

Branch Instructions and their next ones

I have this issue that if a conditional branch instruction (A) has an instruction following it (B), then B will not be executed properly. It will stay in the instruction for only one cycle. In that cycle hold and jump will both be 0.

This makes the Program Counter to jump to the next instruction after one cycle only.

I do not want to change the code in the PC.v file, by adding more ports, but, if it is absolutely necessary, then fine. I believe it is a problem with how I implemented the FSM for the branch instructions (with only 1 state - where I assign the jump and jumpLine values), but I don't know how to modify the FSM to avoid this problem.

Insufficient bitsize for MOV opcode

The MOV opcode is 11 loc_a(7bits) loc_b(7bits). This way of adressing cannot cover 256 lines of data.

One way to fix this would be to use data in registers as locations. That is, formatting the opcode as 11 0000 aaa bbb 000 0.