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A convolutional neural network implemented in hardware (verilog)

License: MIT License

MATLAB 1.16% C 1.38% Python 4.96% Verilog 81.72% Objective-C 9.00% Shell 0.27% HTML 0.33% C++ 1.18%

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hardware-cnn's Issues

Fully Connected Layer

Is every input node multiplied with the same filter values or if each input node is multiplied with different sets of filter values?

about this porject

Hi~ I have some problems about Hardware-CNN, so I hope to get your help.
1、how can I run this project as a demo? it seems that the src files' strcuture is not complete.
2、if the project is no problem, can you give a brief introduction for the net structure?

Thank you very much~

Create single build tool

Create a single script to output the files necessary to synthesize a network in quartus. Because the networks are trained in matlab, the build script will be written in matlab but it will use bash and python scripts that do most of the work.

Writing Feature Map to Buffer

When the convolved and pooled feature maps are written to their buffers, an extra address is written too. this is only a problem if the matrix multiplication reads an extra address (it shouldn't) or if the feature map uses the entire buffer, causing the extra word to be written to address 0.

Macro Names

To Do:

Male each macro name in network_params.h reference the module it is used in.
NN_WIDTH should be replaced with more specific macros for each module since the bit width of each module's input and output will change for things like carry bits. currently the only thing NN_WIDTH describes is the convolution layer input or output width

Readme or steps to run

Hi,
Could you please point me to a readme file for this project or provide me with steps to run this project.

Thanks,
Subhash

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