alfikpl/ao486

The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.

ao486's Issues

How to study the ao486 project?

Hi , I am a newer to FPGA, I major in computer architecture. Recently，I want use the FPGA to prove my some work(focus on pipeline ,especially in decoder), and I find the amazing work - ao486 project. But I have no idea of how to study it, because It is so complex. Is anyone can give me some advise of how to study it.
think you very much

It doesn't boot

I used the BIOS file and other files in the folder 'sd' and all follow your guide. But after choosing floppy image, the screen went black and nothing happened. What the problem maybe? Thanks for your help.
    Best regards,
    Cangyuan Lee

part's wont build

There are some files in the projects that don't exist in git. The processor compiles. But the SoC doesn't.
Perhaps you can check it on a freshly installed machine ?

best wishes

Drum sounds weird in OPL3 in ao486

I played ROL file (song file) on player in ao486. But drum sounds weird. Fix possible?

sd/hdd

could you perhaps add an example using freedos to the git or mail me one ?

i don't grasp the concept. The virtual harddrive would be a partiton ?
Does it have a MBR ? or should i just dd my old dos drive to the sd ?

thanks alot for help, i was using an old quartus version where the qsys was named differently ..

molekel

Performance issues

Hi,

it's very amazing project!
I'm working on port of ao486 to DE10-nano (MiSTer project). It's almost finished and i can already run some benchmarks under DOS.
Currently the system clock of project is 90MHz (100MHz is unstable), and it uses DDR3 memory.

Benchmarks show very slow speed. For example Norton SysInfo shows 14 points while 386DX-33 is 35 points. This is confusing.. 90MHz with 32bit (64bit on DDR3 through bridge) and slower than 386DX-33?

Some benchmark shows that L1 cache is disabled. Is it implemented or simply disabled somewhere?
What is the main bottleneck in performance? Can you give an advise where it can be improved?

Support

Hi,

Would this run on a ALTERA Cyclone IV EP4CE6 FPGA Development Board Kit Altera EP4CE NIOSII ??

Regards

Only find fdboot.img

I have load bios and vgabios successfully. but when load the img file , I only find the fdboot.img, but I did not copy this file, no matter I copy freedos.img or not. It does not work. thanks
sudo dd if=bios_vgabios.dat of=/dev/sdc0 bs=102400 seek=0 sudo dd if=freedos1.1.img of=/dev/sdc0 bs=102400 seek=512

Pin usage ?

According to Readme.md the pin usages is
Total pins : 108 / 529 ( 20 % )
However when I compile using Quartus II Lite 18.1 I get
Total pins : 207 / 529 (39 % )
I have been trying to recompile for a 10 LP dev board 10CL025YU256I7G
and 207 pins will not fit 108 would be fine.
Am curious why the IO bus has been given separate input and output from
the main bus.

Thank you for the excellent work
John Luke

Nios II / main.cpp

Hello alfikpl! I hava noticed that "memcpy(dst_ptr, sector_buf, current_size);" in main.cpp line 291! I also viewed the java source code SDGenerator.java. I found the address "dst_ptr" would equal 0xF0000(BIOS) and 0xC0000(VGABIOS) when Nios application was ran. 0xF0000 and 0xC0000 were writed to file sd.dat through SDGenerator.java! Nios II will copy Bios and VGABios from SD card to location that are pointed by 0xF0000 and 0xC0000. SDRAM's address map region is 0x0800_0000-0x0bff_ffff. They are not in SDRAM. So, how can the ao486 run Bios and VGABios? Can it find and run Bios and VGABios at address 0xF0000 and 0xC0000?
Best regards,
Jerry Zh.

missing define.v?

I'm trying to synthesize the core in Vivado. It pointed out the fact that in rtl/ao486/memory/avalon_mem.v, it's trying to include "defines.v", but a file name defines.v does not exist in that same directory. What's the correct solution? Does verilog/Vivado have the concept of include paths?

Sorry if the answer is obvious, I'm more of a VHDL user than a Verilog user.