Comments (2)
LMN128
commented on July 16, 2024
1
Great. Thanks a lot. I am looking forward to audio implementation.
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sameer
commented on July 16, 2024
Sure! The pixel clock corresponds to what's in CEA61-D. The TMDS clock is always 10 times as fast as the pixel clock.
Here they are for the video modes that I implemented, I'll make sure to add it in the README
- 640x480 (1) @ 60Hz: 25.2MHz
- 720x480 (2,3) @ 60Hz: 27.027MHz
- 1280x720 (4) @ 60Hz: 74.25MHz
- 1920x1080 (16) @ 60Hz: 148.5MHz
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Related Issues (20)
- LCD Bus Compatible Input HOT 4
- Casting that is used in testbench is not in accordance with LRM HOT 1
- How to use in Spartan 6? How to translate to Verilog? HOT 7
- Works on ULX3S (Lattice ECP5) HOT 13
- sawtooth sound output problem HOT 7
- something wrong in audio HOT 6
- implmenting hdl-util/hdmi on a Spartan Edge Accelerator system HOT 1
- Tang Nano 9K HOT 3
- Need help... HOT 19
- Not apply
- IP-less serializer is not working HOT 1
- Source Product Description Infoframe checksum wrong HOT 1
- Distorted audio when 24bits are used HOT 1
- Can't Synthesis on Vivado 2022 HOT 1
- Incorrect Calculation Formula for N in Audio Regeneration HOT 1
- Potential violation of the HDMI 12 pixel minimum control period HOT 4
- Clarify license HOT 2
- DDR instead of LVDS output. HOT 1
- some information HOT 2
- incompatibility with capture devices HOT 2
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