Long time test - OK

[hdl-util]

Long time test - OK

[LMN128]

Hi Sameer, It’s great, thanks a lot. I will check it asap. Jan From: Sameer Puri <[email protected]> Sent: Wednesday, January 8, 2020 5:40 PM To: sameer/verilog-hdmi <[email protected]> Cc: Jan Kucera/8BC <[email protected]>; Author <[email protected]> Subject: Re: [sameer/verilog-hdmi] Long time test - OK (#4) Hi Jan, just wanted to give you an update on this -- I've completed a full first pass on audio and am planning on testing things out today. I'm also looking for some feedback from you on the ideal paradigm for sending audio / other packet data. The way I have it set up right now is: 1. The HDMI module will output a clk_packet that rises at the same time as clk_pixel, every time a new packet is going to be transmitted 2. Use an 8-bit select to choose which packet type you intend to transmit (i.e. 0 for NULL, 1 for audio clock regeneration, 2 for audio samples) 3. If sending audio samples, send them through audio_sample_word which allows for both left and right channels to be transmitted. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#4>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AALFYXC23K3RFHZRQGR3WFDQ4X6WJANCNFSM4JX2HDCQ>.

[LMN128]

Hi Sammer, I see you work very hard on this project, it look very good. I finally going to test audio output today. I looking forward to it. Is possible to send you some questions related to project directly by email, messenger, telegram or other ones, please? Jan Kucera

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________________________________ From: Sameer Puri <[email protected]> Sent: Wednesday, January 29, 2020 4:52:15 AM To: sameer/verilog-hdmi <[email protected]> Cc: Jan Kucera/8BC <[email protected]>; Author <[email protected]> Subject: Re: [sameer/verilog-hdmi] Long time test - OK (#4) I've simplified things a lot now, so there's no need for packet management/buffers anymore. You simply send the audio and its clock into the HDMI module now, the rest is handled for you. module yourfpga_top ( output wire [2:0] tmds_p, output wire tmds_clock_p, output wire [2:0] tmds_n, output wire tmds_clock_n, ); logic clk_original; logic clk_pixel; logic clk_tmds; logic clk_audio; pll pll(.clk_original(clk_original), .clk_pixel(clk_pixel), .clk_tmds(clk_tmds), .clk_audio(clk_audio)); logic signed [15:0] audio_sample_word = 16'sd0; // Since the L-PCM audio is 2-channel by default, this is mono audio. @Always (posedge clk_audio) // Sawtooth wave generator audio_sample_word <= audio_sample_word + 16'sd638; logic [23:0] rgb = 24'd0; // black video logic [9:0] cx, cy; hdmi #(.VIDEO_ID_CODE(3), .AUDIO_RATE(48000), .AUDIO_BIT_WIDTH(16)) hdmi(.clk_tmds(clk_tmds), .clk_pixel(clk_pixel), .clk_audio(clk_audio), .rgb(rgb), .audio_sample_word('{audio_sample_word, audio_sample_word}), .tmds_p(tmds_p), .tmds_clock_p(tmds_clock_p), .tmds_n(tmds_n), .tmds_clock_n(tmds_clock_n), .cx(cx), .cy(cy)); endmodule — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#4>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AALFYXGT7DJUMH4BHP6DBLDRAD4O7ANCNFSM4JX2HDCQ>.

[sameer]

Hi Jan, glad it is working well so far. I haven't had much time lately due to final projects/exams for classes at university. I should be able to work on it this Thursday.

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-------- Original Message --------

On Dec 8, 2019, 04:57, Jan Kucera wrote: Hi, this is only a note. I use this code and make long time test and have to say works very well. Thanks for you work Sameer. I am looking forward for Audio features. How is going with this, please? — You are receiving this because you are subscribed to this thread. Reply to this email directly, [view it on GitHub](#4), or [unsubscribe](https://github.com/notifications/unsubscribe-auth/ACUVICB4CY74Z3P4DA2CX6DQXTHJXANCNFSM4JX2HDCQ).

[sameer]

Hi Jan, just wanted to give you an update on this -- I've completed a full first pass on audio and am planning on testing things out today.

I'm also looking for some feedback from you on the ideal paradigm for sending audio / other packet data, since you have a real-world use case.

The way I have it set up right now is:

1. The HDMI module will output a clk_packet that rises at the same time as clk_pixel, every time a new packet is going to be transmitted (every 32 pixels before the video frame is sent)
2. Use an 8-bit select to choose which packet type you intend to transmit (i.e. 0 for NULL, 1 for audio clock regeneration, 2 for audio samples, etc. listed in HDMI spec)
3. If sending audio samples, send them through the audio_sample_word HDMI module input which allows for both left and right channels to be transmitted.

Let me know what you think.

[sameer]

Hi Jan,
Sorry for the delay, I just got the audio working on my end. I had to write a bunch of testbenches to correct logic/timing mistakes, and my FPGA's 32kHz oscillator isn't working.

Let me know when you have some time to test things out.

[LMN128]

Hi Sameer, Sorry for my delay as well. I am quite busy last days. I did’t have time to make progress of my project. But i shortly look to your work and there is a lot work done. Almoust all souce codes are chaged, some are updeted to System Verilog. This is not problem to me. I like System verilog. Could you shortly explain basis of audio implemetation, please. Eg. Audio clock is gerated from pixel clock or i have to create it outside? Is there still option to use project in backward compatibility with DVI (without audio and other specificies of HDMI), please? Thansk a lot Jan From: Sameer Puri <[email protected]> Sent: úterý 21. ledna 2020 8:15 To: sameer/verilog-hdmi <[email protected]> Cc: Jan Kucera/8BC <[email protected]>; Author <[email protected]> Subject: Re: [sameer/verilog-hdmi] Long time test - OK (#4) Hi Jan, Sorry for the delay, I just got the audio working on my end. I had to write a bunch of testbenches to correct logic/timing mistakes, and my FPGA's 32kHz oscillator isn't working. Let me know when you have some time to test things out. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#4>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AALFYXHYU4Z45LTAACMJYNTQ62OHRANCNFSM4JX2HDCQ>.

[sameer]

Hi Sameer, Sorry for my delay as well. I am quite busy last days. I did’t have time to make progress of my project. But i shortly look to your work and there is a lot work done. Almoust all souce codes are chaged, some are updeted to System Verilog. This is not problem to me. I like System verilog.

Sorry about making so many changes, I was implementing audio in Verilog, but found that unpacked arrays in SystemVerilog would make things a lot more compact and clear.

Could you shortly explain basis of audio implemetation, please. Eg. Audio clock is gerated from pixel clock or i have to create it outside?

Sure -- I'm trying to keep things as simple as possible:

• Audio sample format: signed L-PCM, anywhere from 16-bit up to 24-bit.
• Audio clock: you create it (whether with PLL, or on-board generator) -- can be 32, 44.1, 48, etc. all listed in README
• Sending the samples: keep a circular buffer of samples filled by your audio generator at the rate of audio clock, which will be sent out whenever there is time to send a packet

Here is some example code for sending 16-bit 48 kHz mono audio:

logic clk_original;
logic clk_pixel;
logic clk_tmds;
logic clk_audio;
pll pll(.clk_original(clk_original), .clk_pixel(clk_pixel), .clk_tmds(clk_tmds), .clk_audio(clk_audio));

logic signed [15:0] audio_in = 16'sd0;
@always(posedge clk_audio) // Sawtooth wave generator
begin
  audio_in <= audio_in + 16'sd638;
end

// Signed-ness is ignored here
logic packet_enable;
logic [7:0] remaining;
logic [15:0] audio_out;
circular_buffer buffer(.clk_audio(clk_audio), .clk_pixel(clk_pixel), .packet_enable(packet_enable && remaining > 0), .remaining(remaining), .audio_in(audio_in), .audio_out(audio_out));

logic [15:0] audio_sample = 0;
logic [7:0] packet_type;
@always(posedge clk_audio) // Decides when to send audio packets
begin
  if  (packet_enable) // The output of this clock will decide what kind of packet will be sent
  begin
    if (remaining > 0)
    begin
      audio_sample <= audio_out;
      packet_type <= 8'h02; // Audio Sample Packet
    end
    else
    begin
      packet_type <= 8'h00; // NULL packet -- send nothing since no audio is ready
  end
end

logic [23:0] rgb = 24'd0; // black video
logic [15:0] audio_sample_word [1:0] = '{audio_sample, audio_sample}; // Since the L-PCM audio is 2-channel by default, this is mono audio.

// More ports for this module are not listed
hdmi #(.VIDEO_ID_CODE(3), .AUDIO_RATE(48000), .AUDIO_BIT_WIDTH(16)) hdmi(.clk_pixel(clk_pixel), .clk_tmds(clk_tmds), .rgb(rgb), .packet_type(packet_type), .audio_sample_word(audio_sample_word));

Is there still option to use project in backward compatibility with DVI (without audio and other specificies of HDMI), please?

Yes, everything is still backwards compatible. Let me know if anything doesn't make sense.

[sameer]

I've simplified things a lot now, so there's no need for packet management/buffers anymore.

You simply send the audio and its clock into the HDMI module now, the rest is handled for you.

module yourfpga_top (
  output logic [2:0] tmds_p,
  output logic tmds_clock_p,
  output logic [2:0] tmds_n,
  output logic tmds_clock_n,
);

logic clk_original;
logic clk_pixel;
logic clk_tmds;
logic clk_audio;
pll pll(.clk_original(clk_original), .clk_pixel(clk_pixel), .clk_tmds(clk_tmds), .clk_audio(clk_audio));

logic signed [15:0] audio_sample_word = 16'sd0; // Since the L-PCM audio is 2-channel by default, this is mono audio.
@always (posedge clk_audio) // Sawtooth wave generator
  audio_sample_word <= audio_sample_word + 16'sd638;

logic [23:0] rgb = 24'd0; // black video
logic [9:0] cx, cy;
hdmi #(.VIDEO_ID_CODE(3), .AUDIO_RATE(48000), .AUDIO_BIT_WIDTH(16)) hdmi(.clk_tmds(clk_tmds), .clk_pixel(clk_pixel), .clk_audio(clk_audio), .rgb(rgb), .audio_sample_word('{audio_sample_word, audio_sample_word}), .tmds_p(tmds_p), .tmds_clock_p(tmds_clock_p), .tmds_n(tmds_n), .tmds_clock_n(tmds_clock_n), .cx(cx), .cy(cy));

endmodule

[sameer]

Closing, discussed over email and resolved issues.