hex-five/multizone-fpga

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.

multizone-fpga's Issues

Add Hex Five JEDEC ID to riscv/riscv-openocd

Request addition of Hex Five's JEDEC ID to https://github.com/riscv/riscv-openocd/blob/5d9f48640461fbac5c30958f63a01e666ee64dd4/src/helper/jep106.inc

Clean up repo

Remove branches and clean up / rebase commits

X300 memory map and interrupt mapppings identical to E31

Consider git submodule dependency

Consider changing repo structure to include E300 repo as submodule - rather than fork. So we can easily bump to newer version of the underlying bitstream.

Update README.md

README.md should explain the purpose of this fork, explain diffrences / extensions and point to original documentation rather than replicate it.

First program upload takes long time.

First openOCD upload after power on takes long time (i.e. 106 sec). Subsequent loads work as expected (i.e. 6 sec). Power cycle the ARTY to reproduce the issue.

building failed

I run the commands to clone the repository and start building but failed.
$ make -f Makefile.x300artydevkit mcs
make -C /home/a/mf/multizone-fpga/rocket-chip/firrtl SBT="java -jar /home/a/mf/multizone-fpga/rocket-chip/sbt-launch.jar ++2.12.4" root_dir=/home/a/mf/multizone-fpga/rocket-chip/firrtl build-scala make[1]: enter path“/home/a/mf/multizone-fpga/rocket-chip/firrtl” java -jar /home/a/mf/multizone-fpga/rocket-chip/sbt-launch.jar ++2.12.4 "assembly" /bin/sh: 1: java: not found Makefile:25: recipe for target '/home/a/mf/multizone-fpga/rocket-chip/firrtl/utils/bin/firrtl.jar' failed make[1]: *** [/home/a/mf/multizone-fpga/rocket-chip/firrtl/utils/bin/firrtl.jar] Error 127 make[1]: quit path“/home/a/mf/multizone-fpga/rocket-chip/firrtl” common.mk:38: recipe for target '/home/a/mf/multizone-fpga/rocket-chip/firrtl/utils/bin/firrtl.jar' failed make: *** [/home/a/mf/multizone-fpga/rocket-chip/firrtl/utils/bin/firrtl.jar] Error 2

mcs failes to build (target romgen)

Hey :)

First of all, this error isn't introduced by multizone-fpga rather than by the orginal freedom project. I have already created an issue there, but since you know the project very good as well, I thought you might be able to help :)

I can't get the .mcs file to build, in particular the make target romgen failes with this error:

make -C /home/anton/uni/bachelor/repos/freedom/bootrom/xip romgen
make[1]: Entering directory '/home/anton/uni/bachelor/repos/freedom/bootrom/xip'
dtc -I dts -O dtb -o /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.dtb /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.dts
/bin/riscv64-unknown-elf-gcc -march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"/home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.dtb"' -static -nostdlib -o /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/xip.elf xip.S
/bin/riscv64-unknown-elf-objcopy -O binary /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/xip.elf /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/xip.bin
od -t x4 -An -w4 -v /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/xip.bin > /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/xip.hex
/home/anton/uni/bachelor/repos/freedom/rocket-chip/scripts/vlsi_rom_gen /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.rom.conf /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/xip.hex > /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/rom.v
Traceback (most recent call last):
  File "/home/anton/uni/bachelor/repos/freedom/rocket-chip/scripts/vlsi_rom_gen", line 90, in iterate_by_n
    batch += (next(it),)
StopIteration

The above exception was the direct cause of the following exception:

Traceback (most recent call last):
  File "/home/anton/uni/bachelor/repos/freedom/rocket-chip/scripts/vlsi_rom_gen", line 138, in <module>
    main()
  File "/home/anton/uni/bachelor/repos/freedom/rocket-chip/scripts/vlsi_rom_gen", line 134, in main
    **parse_line(line))
  File "/home/anton/uni/bachelor/repos/freedom/rocket-chip/scripts/vlsi_rom_gen", line 113, in parse_line
    kwargs = {key: try_cast_int(val)
  File "/home/anton/uni/bachelor/repos/freedom/rocket-chip/scripts/vlsi_rom_gen", line 113, in <dictcomp>
    kwargs = {key: try_cast_int(val)
RuntimeError: generator raised StopIteration
make[1]: *** [Makefile:38: /home/anton/uni/bachelor/repos/freedom/builds/e300artydevkit/rom.v] Error 1

My tool versions:

Python 3.9.1
DTC 1.6.0
Vivado v2020.2 (64-bit)
openjdk 11.0.10 2021-01-19
  OpenJDK Runtime Environment AdoptOpenJDK (build 11.0.10+9)
  OpenJDK 64-Bit Server VM AdoptOpenJDK (build 11.0.10+9, mixed mode)
riscv64-unknown-elf-gcc (Arch User Repository) 9.2.0

I'll continue digging around in rocket-chip and try to understand what happens there.

Thanks in advance,
Anton

Update "Requirements" section in README

Hey :)
when I tried building the project, some strange Java errors occured, like "class String" not found and so on.

Only when I looked um the original sifive/freedom repository to find out where to submit my issue I noticed that in the original repo the README is much more detailed, with requirements like Scala, sbt, etc.

In the end my initial error was fixed in a second by installing Scala.

It would be great if you could either reference that there are more requirements to be found in the sifive repo or if you could copy their instructions, so that others can find the relevant information more easily.

Thanks and best wishes