jakubcabal/spi-fpga

SPI master and SPI slave for FPGA written in VHDL

Hi there 👋

I am FPGA engineer in Czech Republic, technology enthusiast, food lover and Linux user (Fedora).

• 🏢 I'm currently working at CESNET z.s.p.o.
• 🎓 My Alma mater: Brno University of Technology
• 📫 How to reach me: Twitter, Telegram
• ⚡ Fun fact: I know my ancestors until the 17th century.

spi-fpga's Issues

Not working on Cyclone II

Hi. I am trying to work with this library using an Altera Cyclone II, working at 50 Mhz.
I use an arduino as master. For debug I set a sclk of 100Khz or similar.
Arduino sends clock and data but miso does not change.
I have set data DIN_VLD to true and set a constant value of DIN input.

Nothing is received.
Thank you

Possible Meta-Stability Issue in Slave Module

The clock signal can potentially trigger meta-stability conditions.

Example is driving SCK from external pin while using significantly faster internal clock. Granted the internal versus external does not matter, however the setup time difference can cause metastable condition to exist. A hardware solution may prevent this using something like a Schmitt trigger.

I have only tried using the slave module on a Lattice Macho XO2. I was using a test signal of about 100kHz and an internal clock of about 133MHz. Simply adding a two register metastability circuit appeared to fix it. (I have only done limited testing with it.) I think this should probably be at least a feature given the amount of control signals that are derived from the ability to detect clock edges.

A question about sclk edge

Hi man,

I have to say that your code looks so comfortable.

I'm a rookie of FPGA designing and have some questions hope that you can help:

1. would that be a problem to shift data on rising edge of CLK together with checking spi_clk_redge_en level? As the spi_clk_redge_en is derived from spi_clk_reg, which is latch on rising edge of CLK as well, which means the spi_clk_redge_en might alter on rising edge of CLK.
2. I have viewed many implementations of SPI slave, some of them use synchronized clock to latch or shift data in/out just like yours, while others use the sclk directly, which one would be better? and why?
3. CAN CS_n be used as RST directly?

spi slave in hw => dout_vld no creating '1' value

Hi again,

After the simulation, I am implementing a simple spi slave in a Altera FPGA. I have wrapped the slave around a top module to assign pins. I have realized that the spi_slave does not rise the dout_vld flag:

I am using the next config:

• CLK of 50Mhz
• SPI SCLK of 5MHz.
• I am using 16bit of data MOSI in each spi transaction.

I have performed a less sofisticated spi_slave_tb gate-level simulation inspired in yours, and looks to be fine.
I have plugged the Signal Tap Logic Analyzer and realize that the main difference is how MOSI behaves, in my case, its idle state is always '1':

Simulation capture:

I don't get why data_vld flag does not rise to '1' after each transaction... 🤔 🤔

Support for different transfer size

Hi,

I have experimented with your code a little. I find it nice to read and learn from. For my purpose I need a larger transfer size (16 bits) perhaps that support for common transfer size (8,16,24,32) can be added?

Maximum SCLK frequency on SPI SLAVE module

Hi, firstly your code is very clear and i'm learning a lot from this, so thanks!

Then I was reading in another issue that with a CLK frequency that is at least twice the SCLK frequency the code works fine.

I was trying to use a CLK at 12 MHz and a SCLK at 4 MHz and i found some problem with the MISO of the SPI SLAVE module.
Pratically the first 1 sended on the MISO remains too much on it and is sampled two times.

I'm using a simplified testbench that i can attach here.

SPI_SLAVE_tb.txt

There is something that I can do to fix this problem?

Question: spi slave sim with just master => slave mosi data transfer

Hi!

I am trying to simulate just a master to slave data transfer through MOSI where the slave transfer nothing to the master.
I was wondering if that's OK, I am trying to usethe SPI_MASTER procedure to generate the SPI waveforms, but I see nothing.

I was wondering if I misundertood some part of the code.
Thanks!

spi slave miso test

Hi again!
I am triying to write from the slave 4x data transfer of 16bit spi data field. This is executed every 5ms.
I am facing an "issue" with the reset state.

In order to handle the spi slave, I am using a state machine that checks the value of din_vld to set the value of din.
So the state machine waits to see an edge of din_vld to set a different value each time.

something like:

p_rising_edge_detector : process(i_clk, i_reset)
  begin
    if(i_reset='1') then
      r0  <= '0';
      r1  <= '0';
    elsif(rising_edge(i_clk)) then
      r0  <= i_din_rdy;
      r1  <= r0;
    end if;
  end process p_rising_edge_detector;
  ---------------------------------------
  edge <= not r1 and r0;
  ---------------------------------------

--------------------------------------------------------------------------------
state_machine_p: process (i_clk, i_reset)
-- Logic to advance to the next state
begin
  if i_reset = '1' then
    state <= s0;
  elsif (rising_edge(i_clk)) then
    case state is
      when s0=>
        if edge = '1' then --wait for slave not busy
          state <= s1;
        else
          state <= s0;
       end if;
      when s1=>
        if edge = '1' then --send first
          state <= s2;
        else
          state <= s1;
       end if;
      when s2=>
      ...
  end if;
end process;

What I see is that the slave is sending a 0x0000 first, and after the data I am sending back to the master.
I am unsure gow to force the slave to not to send this 0x0000 and start with my first 16bit data.

To put it more clear:

The first message I want to send is 0xCAFE, but it is not registered after the reset.
I am not sure how to handle this, as I see that in the first execution I am seeing 5 rising edges of din_rdy and after 4, as expected:

How should I handle it?
Thanks!