joshuaebenezer/fft-cordic-hdl

FFT implementation using CORDIC algorithm written in Verilog.

fft-cordic-hdl's Issues

A question for algorithm

I can't understand that why do the input values of x and y are shifted right by 1 bit, 4 bits and 5 bits respectively, and then summed and fed into the CORDIC operation?Looking forward to your answer，Thanks.

a question

In the simulation encountered the problem of “Error (10028): Can't resolve multiple constant drivers for net "done" at cordic.v(88)
”and “Error (12152): Can't elaborate user hierarchy "butterfly:butterflies1[0].b1|cordic:c1"
It seems that it is not allowed to be repeatedly assigned in the loop in cordic.v.Please advise me what should I do?Thanks a lot.