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axi's Introduction

Hi there, I'm Rishav Kumar ๐Ÿ‘‹

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I'm an ASIC Engineer!!

  • ๐Ÿข Iโ€™m currently working on building next-gen PCIE IPs at NVIDIA
  • ๐Ÿฅ… 2024 Goals: Contribute more to Open Source RTL projects
  • โšก Fun fact: I love to learn new stuff and capture beautiful scapes
  • ๐ŸŒŒ Love to learn and share space-related stuff

Connect with me:

kumarrishav14.github.io kumarrishav14 | Twitter kumarrishav14 | LinkedIn kumarrishav14 | Instagram


Languages and Tools:

Verilog

System Verilog

UVM

Visual Studio Code

Linux

Git

GitHub

Terminal

UVM

UVM




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axi's Issues

Plan development roadmap

Plan out the following things:

  • 1. Functionalities to be included in each release
  • 2. TB architecture development
  • 3. Feature Extraction
  • 4. Coverage descriptions

Slave

Following things need to be implemented

  • Driver - Will drive the slave signals
  • Monitor - Will monitor the interface.

Sequence

2 base sequences to be implemented:

  • Write Sequence - Will generate write transaction packets
  • Read Sequence - Will generate read transaction packets

axi slave hanging

Hi
I am adopting an axi slave as a memory in our environment, but it didn't exist and was hanging when test cases finished.

Master

Master will have following components:

  • Write Sequencer
  • Read Sequencer
  • Driver
  • Monitor

Both sequencers will run parallelly to create read and write simultaneously, as AXI has dedicated read and write channel

RDATA does not return from axi_m_driver

Hello. Why are you choose the Sequence-Driver API "get_next_item() followed by item_done()" ?
Don't you think would it be better to use "get(req) followed by put(rsp)" model (this naming I get from UVM cookbook)?
With "get(req) followed by put(rsp)" model you can return to sequence read data and bresp status.

Sequence Item

Development of AXI transaction packet which will hold all the respective data that needs to be sent to the master.

Hello,

How can I run this on EDA playground?

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