lnls-dig / bpm-gw Goto Github PK

Repository containing the gateware for the Beam Position Monitor project

License: GNU Lesser General Public License v3.0

Python 0.72% VHDL 36.36% C 44.07% Shell 0.21% Tcl 4.77% C++ 1.11% Assembly 0.45% Makefile 0.32% MATLAB 0.20% HTML 10.25% SystemVerilog 0.36% Verilog 0.59% Stata 0.60%

afc amc fmc fpga bpm

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bpm-gw's Issues

[wb_acq_core] Check lmt_curr_chan_id signal and its use

Problem: Some internal modules sync lmt_curr_chan_id signal with fs_clk_i, which is wrong, as the lmt_curr_chan_id signal is sync'ed with ext_clk_i. This does not apparently causes problems, as this signal are static and changed only at the beginning of each acquisition.

[wb_fmc130m_4ch] Each 77 samples is repeated on acquisition

Problem: Each 77 ADC samples gets repeated on acquisition. This doesn't happen when using the ADC test data set, generated on the FMC130M_4CH module. So, the problem is likely related to the fmc130m_4ch module itself

[top] Add remaining DSP signal paths to acquisition core

Problem: We need to acquire all of the DSP signal paths to validate it properly.

Solution: Simply add more channels to the ACQ module

[fmc516] fix multiple MMCM primitives in adc_clock.vhd

Issue by lerwys
Thursday Mar 21, 2013 at 01:30 GMT
Originally opened as lerwys/bpm-sw-old-backup#18

[soon-to-be fmc-port] Add g_with_bufio and g_with_bufr

Issue by lerwys
Tuesday Aug 27, 2013 at 02:15 GMT
Originally opened as lerwys/bpm-sw-old-backup#24

This will allow selecting if we want the incoming clock to be routed to BUFIO and/or BUFR primitive. This effectively will clock an IDDR primitive with BUFIO and local FPGA logic with BUFR. Later, all data will be synch'ed to a global reference clock.

Cauting is taken to ensure safe passage from one clock domain to another with Async FIFOs

[fmc516] Delay the falling edge data from the IDDR primitive

Issue by lerwys
Saturday Mar 16, 2013 at 15:14 GMT
Originally opened as lerwys/bpm-sw-old-backup#13

There is an issue regrading the sampling the data from the ISLA216 with the IDDR primitive. There needs to be an investigation to why this happens, but the solution is very simple...

[wb_acq_core] Cannot acquire less than f_log2(<output data width>/<input channel data width>) samples

Problem: Due to the difference between input data width (acquisition core) and output data width (DDR core) we must acquire at least f_log2(output data width/input channel data width) samples. In our case, this translates to 8 samples for ADC and ADCSWAP and 4 samples for everything else.

Solution: Just force the software to acquire f_log2(output data width/input channel data width) samples.

[CLOSED] Implement ADC Reset and Reset Clk Div

Issue by lerwys
Friday Nov 30, 2012 at 11:31 GMT
Originally opened as lerwys/bpm-sw-old-backup#3

There is a need to reset the ADCs and the clock output clock reset (for synchronization of
multiple ADC chips).

Also, they need to be software controllable.

[pcie_core] [dbe_bpm_dsp] XDC files references nets Vivado can't find

PROBLEM: Some constraints in pcie_core.xdc and dbe_bpm_dsp.xdc are commented and marked as FIXME because Vivado can' t find the proper nets after migration from ISE. These constraints do not prevent proper operation of the core, but may be leading to inefficiencies during implementation.

Possible Solution: This is probably caused by the nets being differently referenced in Vivado due to hierarchy. Finding a proper way to reference the same net using the new XDC features should solve the problem.

[CLOSED] [FMC516] Check SPI communication

Issue by lerwys
Friday Mar 01, 2013 at 20:26 GMT
Originally opened as lerwys/bpm-sw-old-backup#11

Especially with SPI 3-wire mode

[CLOSED] Insert CLOCK_DEDICATED_ROUTE=FALSE constraint to .ucf

Issue by lerwys
Tuesday Dec 04, 2012 at 12:50 GMT
Originally opened as lerwys/bpm-sw-old-backup#5

"The CLOCK_DEDICATED_ROUTE=FALSE workaround is typically for source clocks which are not assigned to global clock input pins -- a completely different problem."

This could be the issue related to driving clock buffers from non GCLK pins.

[all] Implement SDB-1.1 structures

Problem: Often, we need to know which firmware version we are running.

Solution: So, using SDB-1.1,which already support integration records, would solve the issue neatly

[fmc-adc-common] Fix BUFIO/BUFR/BUFG clk generation

Issue by lerwys
Friday Aug 30, 2013 at 04:14 GMT
Originally opened as lerwys/bpm-sw-old-backup#25

Fix BUFIO/BUFR/BUFG clk generation in adc_clk.vhd entity, when 7SERIES FPGAs are selected

[fmc516] Implement synchronization between all data chains with a single clock domain

Issue by lerwys
Monday Mar 18, 2013 at 19:50 GMT
Originally opened as lerwys/bpm-sw-old-backup#16

The default behavior of the module is to clock the data with 2 clocks. In this way,
we have to sync the data of all 4 data chains to a single clock. By default, the first used clock will be used for this.

[CLOSED] Replace IBUFGDS to IBUFDS

Issue by lerwys
Tuesday Dec 04, 2012 at 02:15 GMT
Originally opened as lerwys/bpm-sw-old-backup#4

These are the same primitive, but the former instructs the mapper to use only global clock nets
(GCLK pins). BUT, as we know, we need to use non global clock nets in order to use BUFIO/BUFR primitives.

This possibly causes the error:

"ERROR:Place:1119 - The I/O components "adc_clk1_p_i" and "adc_clk1_n_i" are the
P- and N-sides of a differential I/O pair. The component "adc_clk1_p_i"
needs to be placed in a IOBM site and component "adc_clk1_n_i" in the
adjacent IOBS site within the same I/O tile. The following issue has been
detected:
Some of the logic associated with this structure is locked. This should cause
the rest of the logic to be locked. A problem was found at site BUFR_X0Y3
where we must place IOB adc_clk1_n_i in order to satisfy the relative
placement requirements of this logic. It is not legal to place this component
in this site. "

[wb_fmc130m_4ch] Add switching clock through MMCX connector

Issue by lerwys
Tuesday Jun 24, 2014 at 16:28 GMT
Originally opened as lerwys/bpm-sw-old-backup#32

[wb_acq_core] Add multiple "simultaneous" acquisition paths

Issue by lerwys
Wednesday Jun 04, 2014 at 19:17 GMT
Originally opened as lerwys/bpm-sw-old-backup#31

There is a need to have multiple acquisition paths acquiring data simultaneous,
in a multiplexed way.

This is the traditional use case for our case, in that 1 AFC handles 2 BPMs signals.
So, at least we must decouple the acquisition paths from the 2 different BPMs

[all] Unify SDB descriptors.

Issue by lerwys
Wednesday Apr 03, 2013 at 19:47 GMT
Originally opened as lerwys/bpm-sw-old-backup#20

Add them to wishbone_pkg.vhd in general cores?

[ddr3-core] Implement a DDR3 core wrapper for Xilinx MIG

Issue by lerwys
Tuesday Apr 09, 2013 at 17:41 GMT
Originally opened as lerwys/bpm-sw-old-backup#21

It is necessary a wishbone wrapper to Xilinx MIG generated core.

In this way, we can store the large ammounts of DSP data.

useful links:

http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_92/ug406.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf
http://www.ohwr.org/projects/ddr3-sp6-core/wiki

[dbe_common] [clock_driver] Reset synch MAX_FANOUT attribute must be reviewed

Problem: Vivado MAX_FANOUT attribute is now a integer and a hard limit - you must give a number and it will be strictly followed by the tool. The REDUCE attribute was deprecated, and to give the tool a soft-limit, you must set it outside the VHDL, in the project properties according to UG901. Check FIXME tags in files reset_synch.vhd and xlclockdriver.vhd.

Possible solution: Manually find a good number for MAX_FANOUT, or maybe use a constraint to nod the tool in the right direction.

[fmc516] Fix reserved register fields

Issue by lerwys
Monday Mar 18, 2013 at 18:26 GMT
Originally opened as lerwys/bpm-sw-old-backup#15

It should be Read-Only from the wishbone side and read as 0's!

[fmc-adc-data] Check registers in the datapath to ease timing

Issue by lerwys
Thursday Sep 19, 2013 at 00:18 GMT
Originally opened as lerwys/bpm-sw-old-backup#27

Consider removing it or improving this part of the code

[wb_acq_core:acq_fc_fifo] Optimize Flow Control Buffer

Problem: As of now, we are using FFs to serve as circular buffer for data words. However, the data word width can get as large as 1024 bits and 4 to 8 words depth, accounting for a lot of resources.

Solution: Change circular buffer to a DPRAM

[fmc516-sw] Support for multiple fmc516 cores (and boards...)

Issue by lerwys
Monday Mar 18, 2013 at 18:01 GMT
Originally opened as lerwys/bpm-sw-old-backup#14

Implement a generic structure to support multiple instances of the fmc516 core, for example.

A simple way would be to create a generic identification structure in which the drive functions would poll in order to determine the correct core (which SPI, I2C, etcc) core to act

[emb-sw] Consider moving the emb-sw folder to another git repository

Issue by lerwys
Wednesday Sep 18, 2013 at 02:38 GMT
Originally opened as lerwys/bpm-sw-old-backup#26

Then this git repository could be reference as a sub-module in bpm-sw

[wb_fmc130m_4ch] ADC clock current delay value not used

Problem: The current ADC clock delay used in the Delay primitive is not used. We only output the current delay for the data channels. This can cause confusion for the software, as the value read in the registers will not be the same as the value just written. This does not produce wrong results, but is confusing on readback tests, for instance.

Possible solution: Output the current ADC clock delay in another Wishbone register.

[CLOSED] Reorganize the dbe_bpm_fmc516 top files

Issue by lerwys
Wednesday Dec 12, 2012 at 16:25 GMT
Originally opened as lerwys/bpm-sw-old-backup#7

There is a mix in this folder, as this synthesis test is not under development yet!
I think the best way to correct this is to create the synth test in the wb-fmc516-devel branch
and leave it untouched in the other ones.

[fmc516] Check ADC clock & MMCM values

Issue by lerwys
Friday Mar 01, 2013 at 20:25 GMT
Originally opened as lerwys/bpm-sw-old-backup#10

Reimplement emb-sw fmc structures!

Issue by lerwys
Friday Jul 05, 2013 at 02:30 GMT
Originally opened as lerwys/bpm-sw-old-backup#23

It is necessary to improve and make a more generic approach to the FMC boards

[fmc-516] Clean wb_fmc516 delay interface

Issue by lerwys
Wednesday Apr 10, 2013 at 01:32 GMT
Originally opened as lerwys/bpm-sw-old-backup#22

The interface between the register core and the var_loadable/variable delay register is very confusing. Fix it!

[CLOSED] [fmc516] Select the appropriate delays to clock and data coming from ADC

Issue by lerwys
Tuesday Dec 04, 2012 at 20:17 GMT
Originally opened as lerwys/bpm-sw-old-backup#6

There is a timing violation in that 1.4 acquisition window is not sufficient for IDDR, as reported
by timing analyzer.

Calibrate the delay from clock and data to match them.

[CLOSED] Fix wrong xwb_fmc516 component declaration in custom_wishbone.vhd file

Issue by lerwys
Thursday Dec 20, 2012 at 00:39 GMT
Originally opened as lerwys/bpm-sw-old-backup#8

It's just what it is described in the title...

[wb_acq_core] Core can hang the DDR3 grant line forever

Problem: The acquisition core does not have any means of releasing the DDR3 grant line if anything wrong happens. This can make the DDR3 read/write unusable for any other module in the system.

Possible Solutions: Maybe some sort of timeout mechanism should be added to the acquisition core. Another approach, more complex but cleaner would be add a smarter arbiter for multiplexing access to DDR3.

[pcie-core] Fix missing signal

Issue by lerwys
Wednesday Dec 04, 2013 at 01:12 GMT
Originally opened as lerwys/bpm-sw-old-backup#29

We should always test our designs before committing it!

/home/lerwys/Repos/bpm-sw-test-pcie/hdl/top/pcie/top_ml605.vhd" Line 183: Formal port/generic <rst_act_low> is not declared in <bpm_pcie_ml605>

[wb_acq_core] Fix unsafe start flag

Problem: The Acquisition Core start flag always triggers the logic, regardless if we are in the middle of a transaction or not.

Solution: Add another register to check if we are in the middle of a transaction. If we are, simply don't allow the user to start an acquisition.

[fmc516] Implement automatic idelay selection

Issue by lerwys
Tuesday Mar 19, 2013 at 16:50 GMT
Originally opened as lerwys/bpm-sw-old-backup#17

It is necessary o module to implement automatic delay calibration, as it is not pratical nor
robust to manually input them.

[pcie_core] Cannot access DDR data from high address

Problem: We can't read data from DDR from pages larger than 10-bits.

The problem appears when I try to read the DDR memory from AFCv3 through
PCIe. As I'm aware the DDR size is 4 GB (2^30 words of 32 bit = 4GB), right?

With that in mind I'm trying to read from DDR page 896, for instance. This gives us
1110000000 in binary, which are 10 bits. So far, so good.

When I try to read from DDR page 1152, which is 10010000000 (11 bits) in binary,
I don't get any valid data, just garbage.

Having a look at rx_MRd_Channel.vhd, which is located in https://github.com/lnls-dig/bpm-gw/blob/devel/hdl/modules/pcie/common/rx_MRd_Channel.vhd (I don't know if this is the
right place to look for this issue) file I see the following lines where sdram_pg is used:

392 pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)                  
393   <= sdram_pg(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT-C_DDR_PG_WIDTH downto 0) &
394       m_axis_rx_tdata_r1(C_DDR_PG_WIDTH-1+32 downto 0+32);
...
412 pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)       
413   <= sdram_pg(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT-C_DDR_PG_WIDTH downto 0) &  
414       m_axis_rx_tdata_r1(C_DDR_PG_WIDTH-1 downto 0);

If my math is correct sdram_pg(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT-C_DDR_PG_WIDTH downto 0) translates to sdram_pg(9 downto 0), which has only the 10 LSB.

[wb_acq_core] Implement channel properties over Wishbone

Problem: There is a need to know which acquisition channels are valid, so we could avoid hardcoding this value in software.

**Solution:**A good approach would be to export the valid channels, as well as its properties over Wishbone. With this, we would be able to read this and check accordingly, as mentioned on github issue lnls-dig/bpm-sw#21

[ebone] Add etherbone support

Issue by lerwys
Wednesday Nov 28, 2012 at 20:22 GMT
Originally opened as lerwys/bpm-sw-old-backup#1

It would be nice and very useful to support etherbone core from ohwr repository (http://www.ohwr.org/projects/etherbone-core).

By doing this, "real " testing could be done easily and scripts could be set up for
executing them automatically.

[ddr3_core] Missing Vivado project file

Problem: The Vivado DDR 2.3 core .xco file is missing from the project.

Solution: Regenerate the Vivado project and include the .xco file

[top,syn] sanitize project folders

Problem: Top projecct names are very long like dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3 and not much descriptive.

Solution: Remove all outdated top modules and rename the current one to a suitable name

[dsp-devel][fmc516] ADC Data appears to be off by one cycle

Issue by lerwys
Thursday Mar 28, 2013 at 19:37 GMT
Originally opened as lerwys/bpm-sw-old-backup#19

The ADC data channels 1 and 2 seems to be 1 clock out of sync with data channels 0 and 3.

[wb_acq_core] Cleanup core and implement missing features

Issue by lerwys
Friday Mar 07, 2014 at 17:47 GMT
Originally opened as lerwys/bpm-sw-old-backup#30

It is necessary to cleanup the wb_acq_core and implement the missing features like
external data-driven triggered acquisitions

[wb_acq_core] Acquisition FIFO gets full when ext_clk_i is lower than fs_clk_i

Problem: If the write FIFO clock is higher than the read FIFO clock, and the interfaces are almost always reading/writing through the FIFO, eventually the FIFO will become full and we will start losing data. We didn't have this problem with the Virtex6, because the ext_clk_i was 200 MHz (2:1 DDR3 operation). Now, with Artix7, we have the ext_clk_i as 100 MHz (4:1 DDR3 operation).

Solution: However, the DDR3 interface is 256 bits, for Virtex6 and Artix7, and the acquisition FIFO is at most 64 bits. With this way, we can implement a multiple FIFO approach, in that each valid input data we write in a different FIFO and waits for 256 bits to accumulate.

[CLOSED] change SPI three mode interface to miso/mosi/out_en

Issue by lerwys
Saturday Mar 02, 2013 at 00:04 GMT
Originally opened as lerwys/bpm-sw-old-backup#12

[ethernet/ebone] Implement mux for ethernet packages?

Issue by lerwys
Thursday Dec 20, 2012 at 02:08 GMT
Originally opened as lerwys/bpm-sw-old-backup#9

Would it be viable to implement a mux in order to separate between etherbone packages and
other ones?

This is done for the white rabbit design. Specifically for the wr-core in which etherone packages
are redirect to etherbone and other messages to the rest of the FPGA fabric.

Study this possibility