m47812/hdl_converter

A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.

hdl_converter's Issues

Module crashes when using comment as first line

Example of problem

module test
#(
parameter myParam1 = 12,
parameter myParam2 = 2
)
(
//==========> !!!!THIS COMMENT IS A PROBLEM!!!! <<==============
input wire clock, //No problem
input wire reset,
//This comment is fine
output wire [7:0] busOut,
inout wire someSignal
//This is also ok
);

Problems when using "," in comments

Verilog uses "," as a separate character. When also using "," in the signal description comments the separation by "," does not work. Error was attempted to fix with the following method to clean the split. It was Removed again because it leads to other possibly more severe issues in the last signal which does not have a comma in Verilog. A Better solution would be to rebuild separate elements and use a different method to separate the elements.

        /// This Function Cleans splits that happend from comments containing a separation charracter like "," 
        /// that is used in code.
        /// </summary>
        /// <param name="input">A string splited by the separation character of the HDL language (Verilog --> ,)</param>
        /// <param name="commentChar">The Syntax for a Comment in the HDL (Verilog --> "//")</param>
        /// <returns>the cleand verion of the input data</returns>
        public static string[] cleanSplitedElements(string[] input, string commentChar)
        {
            if (input.Length == 1) return input;
            List<string> correctedSplited = new List<string>();
            for (int i = 0; i < input.Length - 1; i++)
            {
                if (input[i].Contains(commentChar) && !input[i].Contains(System.Environment.NewLine))
                {
                    correctedSplited.Add(input[i] +" "+ input[i + 1]);
                    i++;
                }
                else
                {
                    correctedSplited.Add(input[i]);
                    if(i == input.Length - 2) correctedSplited.Add(input[i+1]);
                }
            }
            return correctedSplited.ToArray();
        }

Instantiation name placed wrong

For instantiations with parameters in Verilog.
The instance name is currently paced right after the module name but should be between parameters and IO Ports.

Should be:

mymodule
#(
//Some Parameters
)
 inst_mymodule
(
//Some IOs
)

Currently is:

mymodule inst_mymodule
#(
//Some Parameters
)
(
//Some IOs
)

Support for direction outside of module Port declaration

The following Verilog syntax is also common e.g. IP block header. Support for this format should be added.

module some_ip(A, B, CLK, S)
  input [27:0]A;
  input [27:0]B;
  input CLK;
  output [27:0]S;
endmodule

signed is removed in conversion

The signed type modification is ignored in Verilog.

output reg signed[5:0] myWire,

Unsupported Syntax versions for Verilog

The Following Syntax versions lead to problems with the decoding mechanism.

reg instead of wire:
output reg signal_valid

Debug Wires:
(* mark_debug = "true" *) input wire valid_signal0,