muhammadaldacher / modeling-of-10-bit-pipeline-adc-and-10-bit-dac Goto Github PK
View Code? Open in Web Editor NEWThis project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.