Related Issues (20)
- [BUG] MIE Supervisor Bits not RO if S is not present HOT 3
- [BUG] AXI bus trouble with write-back cache HOT 1
- [BUG] MIP Supervisor Bits not RO if S is not present HOT 1
- An overlap with "ZEXTH" instruction HOT 4
- [BUG] Unexpected Behavior in M Extension Instructions with Identical Operands HOT 2
- Dependency between uvme_cva6_config_covg and localparam of config package HOT 1
- [BUG] PMPCFG WARL behavior HOT 8
- [BUG] uvme_exception_covg and uvme_illegal_instr_covg not compliant LRM
- Use only cva6_cfg parametrization structure
- ZCB RISCV compilor in smoke-gen_tests HOT 5
- Parametrization: dependencies with HPDCache HOT 4
- DRAM and AXI interconnect throughput with single-beat master HOT 1
- How to flush the data cache? HOT 1
- [BUG] Hardcoded 300s Timeout Issue during VCS Compile/RTL Simulation in cva6.py HOT 2
- what the flag of the RV_test pass or failed with spike
- [BUG] riscv-arch-tests no longer executed in CI HOT 1
- [BUG] Allowing illegal access to addresses outside the PMP range and memory boundaries. HOT 6
- [BUG] External supervisor mode interrupt HOT 1
- [BUG] Unexpected Rounding Behavior During fsqrt.d Execution HOT 2
- [BUG] Incorrect Accumulation of ‘OF’ Flag in fflags After Executing fsqrt.d on Infinity HOT 1
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from cva6.