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axi2apb's Introduction

AXI to APB bridge

This repository has been archived. A fully compliant replacement for this module can be found in pulp-platform/axi.

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axi2apb's Issues

PENABLE Signal out of spec.

The PENABLE signal is driven high during the SETUP state of an APB transfer. This should be driven during the ACCESS state according to APB spec.

See here for a version of the APB spec.

assign PENABLE = write_req | read_req; and in APB node:

assign psel_o[i] = (paddr_i >= START_ADDR_i[i]) && (paddr_i <= END_ADDR_i[i]);
if( psel_o[s_loop1] == 1'b1 )
begin
penable_o[s_loop1] = penable_i;

Will evaluate to PSEL and PENABLE driven high in the same APB clock cycle. There should be one clock cycle between PSEL = 1'b1 and PENABLE = 1'b1.

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