Comments (4)
YenHaoChen
commented on August 23, 2024
@jscheid-ventana @jjscheel
Friendly reminder
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pdonahue-ventana
commented on August 23, 2024
"The mhpmeventn registers are WARL registers" so presumably any bit that's not supported would be hardwired. Maybe that should be explicit as it is in some other specs. @gfavor
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gfavor
commented on August 23, 2024
I agree. The definition of WARL requires that a read of a WARL bit always returns a "legal" value - where "legal" values are "supported" values. Hence, if the bit's functionality is not supported, then the only "legal" value is zero.
Also note that writing all zeroes to mhpmeventX must represent "no event". So hardwiring an unsupported bit to one would be inconsistent with this.
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YenHaoChen
commented on August 23, 2024
Thank you
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Related Issues (10)
- Integration into the Priv Specification has begun. HOT 2
- Privilege mode requirements
- Mcounteren relevance in reading scountovf HOT 1
- Can software disable LCOFI by setting mhpmeventx.OF to 1? HOT 2
- Interrupt Overflow HOT 2
- Ratified Version Document HOT 9
- Does hardware automatically clears OF bit on writing the counter? HOT 2
- What is the value of the OF bit after an overflowing CSRW clearing the OF bit? HOT 2
- Can mip/sip CSR write pend count overflow interrupt?
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