riscv/riscv-count-overflow

riscv-count-overflow

Working draft of the proposed RISC-V Sscofpmf extension.

riscv-count-overflow's Issues

Interrupt Overflow

Hello, I have a question, the Sscofpmf spec why don't support the interrupt overflow of cycle and instret?

Can software disable LCOFI by setting mhpmeventx.OF to 1?

@pdonahue-ventana @gfavor
The OF bit is an overflow status and interrupt disable bit.
Can software write 1 to the OF bit to disable the interrupt?


Thank you

Integration into the Priv Specification has begun.

Noet that I've began work to integrate this spec as a chapter within the Privileged Specification. I'll add a PR link once it's issued.

Writability of SINH, UINH, VSINH, and VUINH when unsupporting corresponding modes

Hello,

Are the SINH, UINH, VSINH, and VUINH of mhpmevent CSRs RW when the corresponding mode unsupported?
For instance, if the S-mode is unsupported, is the mhpmevent.SINH still RW or read-only 0?

Thank you
Best regards,
YenHaoChen

Mcounteren relevance in reading scountovf

Hi,
The spec says,

In M and S modes, scountovf bit X is readable when mcounteren bit X is set, and otherwise reads as zero.

Should it be the case that the mcounteren bit only matters while reading scountovf from S mode ? And scountovf should always give the true value on reading in M mode irrespective of the corresponding mcounteren bits.
Asking this since mcounteren controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode.

Thanks

Ratified Version Document

Sscofpmf is ratified in 2021. However, the version of document is 0.5.2-frozen. Does the ratification bump the version to 1.0-ratified?

What is the value of the OF bit after an overflowing CSRW clearing the OF bit?

Hello @gfavor,

I want to understand the corner case behavior of the OF bit.

An instruction causing the HPM counter to overflow will set the OF bit. Additionally, a CSRW instruction can clear the OF bit. Consider the counting event includes CSRW instructions. What is the value of the OF bit after an overflowing CSRW clearing the OF bit?

The Zicsr specification says that the CSRW takes priority over the side effects of instruction execution. Is setting the OF bit a side effect of an overflowing instruction?

Thank you.

Best regards,
Howard (Yen-Hao) Chen

Does hardware automatically clears OF bit on writing the counter?

Hello @gfavor ,

Does hardware automatically clear OF bit and enables overflow interrupt generation on writing the counter to a starting value? More specifically, will a CSR instruction explicitly writing mhpmcounter3 also implicitly clear mhpmevent3.OF?

Thank you.

Can mip/sip CSR write pend count overflow interrupt?

The specification says (in section 1.2):

LCOFIP is read-write in mip and reflects the occurrence of a local count overflow interrupt request resulting from any of the mhpmeventn.OF bits being set.

Does this mean that M-mode software can set this bit to 1 in mip to make LCOFIP pending? And if so, can it be set pending when not delegated to S-mode, thus triggering an immediate M-mode interrupt? Similarly, can S-mode set this bit to 1 in sip if the interrupt has been delegated, potentially also triggering an immediate S-mode interrupt? This behavior is different from that specified for other writeable bits in mip (e.g. SSIP) where writes can pend interrupts for lower exception levels only.

Thanks.

Privilege mode requirements

Does Sscofpmf require supervisor mode to be implemented? Based on the name, that seems like the case.