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ABACUS is a tool for approximate logic synthesis

License: Other

Verilog 38.94% Python 1.06% Stata 1.56% C++ 1.19% Makefile 0.16% C 55.64% Yacc 0.92% Lex 0.31% Shell 0.22%
logic-synthesis verilog synthesis approximate-computing approximate-circuits

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soheilhme mfkiwl witschen-hub drheli yuzy111

abacus's Issues

folder is missing

The QOR file in the fir folder will report an error
**temp=[0]*len(groundtruthData[x])**Error will be reported here
The qor file in the perceptron folder is missing
I read your article，
I want to know if I want to set the accuracy threshold of block matching to 28dB,
python abacus.py [TESTBENCH_FOLDER] [design_file_to_be_approxamted] min_accuracy_threshold(0-100)
How much should I set the min_accuracy_threshold(0-100) here

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