schoeberl/chisel-book

Digital Design with Chisel

chisel-book's Issues

Broken link to test benches reference

https://github.com/schoeberl/chisel-book/blob/master/chisel-book.tex#L1339

Looks like link reference to test benches is out-of-date.

Possible bug in MemFifo in fifo.scala

HI,

I believe there is a bug in the MemFifo implementation in fifo.scala. It is shown the figure below. If the FIFO gets two consecutive words (while empty) during which it can produce output (deq.ready is high), then the second word will never be output. This is because the "valid" state will set emptyReg to true (will override writes decision since it comes after it in code), so back in Idle state, it will get stuck (since there are no more writes setting emptyReg to false.

My solution is to put the write handling block (below), after the read handling switch statement.
when (io.enq.valid && !fullReg) {
mem.write(writePtr, io.enq.bits)
emptyReg := false.B
fullReg := nextWrite === readPtr
incrWrite := true.B
}

I haven't fully tested it but it seems to work now.

Typo in Figure 7.4: A Mealy type finite state machine

It says Ouput logic instead of Output logic.

chisel-book/figures/mealy.graffle

Line 452 in b1fd3c2

\f0\fs24 \cf0 Ouput\

What do we do if we still want partial bulk connection

For 4.3 Bulk Connections, the If a name is missing, it is not connected. seems to be deactivated already. What do we do if we still want to use <> for partial bulk connection? i.e., for the same fetch decode execute as before?

No makefile

Hello,

Have you got a Makefile to generate the pdf ?
It's easier to read a pdf than *.tex collection ;)

thx

Build mobi version for Kindle

Is it possible to add to the build process the generation of a .mobi file for Kindle?

SyncReadMem example with read enable

Unlike Mem, SyncReadMem has a read method with two arguments:

def read(x: UInt, en: Bool)

I could not find any examples of this method being used in the book. I think "1 KiB of synchronous memory" example should have a read enable input.

class Memory() extends Module {
  val io = IO(new Bundle {
    val rdEna = Input(Bool())
    val rdAddr = Input(UInt(10.W))
    val rdData = Output(UInt(8.W))
    val wrEna = Input(Bool())
    val wrData = Input(UInt(8.W))
    val wrAddr = Input(UInt(10.W))
  })

  val mem = SyncReadMem(1024, UInt(8.W))

  io.rdData := mem.read(io.rdAddr, io.rdEna)

  when(io.wrEna) {
    mem.write(io.wrAddr, io.wrData)
  }
}

How to run test in a terminal

In the section 5.2.1, you introduce peekpoketester and write that "When you run the test, you will see the results printed to the terminal...".
And I am exactly wondering how do you run the test in a terminal? With which command? When I run "sbt run", it tells me
[error] java.lang.RuntimeException: No main class detected.
[error] at scala.sys.package$.error(package.scala:30)
[error] stack trace is suppressed; run last Compile / bgRun for the full output
[error] (Compile / bgRun) No main class detected.

Index

I have the paperback version of this book, it's useful but an Index is missing. For paper version index is really usefull, I don't know if its hard to do ?

Lonely semicolon

There is a singular semicolon in the first Chisel example

chisel-book/src/main/scala/Hello.scala

Line 24 in 616ae0a

val CNT_MAX = (50000000 / 2 - 1).U;

Is this a typo? Seems odd that this line needs one when the others don't.

multi clock memory

The multi-clock memory gives a warning with Chisel 5.0.2:

[deprecated] @[src/main/scala/MultiClockMemory.scala 26:21] (3 calls): The clock used to initialize the memory is different than the one used to initialize the port. If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0

Question about arbitrateSimp

Hi @schoeberl,

In arbitrateSimp, regEmpty is updated to true when (out.ready), but what if out.ready is true when regEmpty is true?

The following test fails while I think it should pass:

class ArbiterTester extends AnyFlatSpec with ChiselScalatestTester {
  "arbiter" should "work" in {
    test(new ArbiterSimpleTree(2, UInt(4.W))) { dut =>
      dut.io.in(0).valid.poke(true)
      dut.io.in(0).bits.poke(14.U)
      dut.io.in(1).valid.poke(false)
      dut.io.out.ready.poke(false)
      dut.clock.step()
      dut.io.out.ready.poke(true)
      dut.clock.step()
      dut.io.out.valid.expect(true) 
      dut.io.out.bits.expect(14.U) 
    }
  }
}

Please help advice, thanks!

is there any known technical reason why the book has no table of contents in PDF?

https://superuser.com/questions/219874/how-to-create-pdfs-with-a-left-pane-that-has-table-of-contents

WireInit

WireInit should not be in the Chisel book.
It is present on page 179 twice.

Tiny misspelling (or missing words?) Vec section

Hi,
Very minor problem - page 19, section 2.4.2 - Vec

A Vec is used for three different purposes: (1) dynamic addressing in hardware,
which is a multiplexer; (2) a register file, which includes multiplexing the read and
generating the enable signal for the write; (3) parametrization if the number of ports
of a Module. For other collections of things, being it hardware elements or other
generator data, it is better to use the Scala collection Seq.

I was skimming through the book and this threw me off. I assume the "if" should be "of", or could it be that some words are missing?

Paperback book index has wrong page numbers

Hi!

I have the paperback version, however, I've just noticed that the index at the end of the book has wrong page numbers.

For example, ALU is listed to appear on page 56 and 213. These are the numbers for the PDF version; should be page 58 and 216 for the physical book.

reference to non-existing testing chapter

It looks like a chapter was removed but is still referenced:

chisel-book/chisel-book.tex

Line 1249 in c467bfb

in Chapter~\ref{chap:testing}.

Conditional Updates Priority

There is something not clear in your good examples

https://github.com/schoeberl/chisel-book/blob/master/src/main/scala/Flasher.scala#L65-L74
https://github.com/schoeberl/chisel-book/blob/master/src/main/scala/Flasher.scala#L126-L127
https://github.com/schoeberl/chisel-book/blob/master/src/main/scala/Flasher.scala#L134-L143

In the above examples, a hardware objects(timerReg, cntReg) are updated by multiple(two) conditionals
It is confusing for beginners including me
You are better to mention Conditional Updates Priority somewhere in your book