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License: Apache License 2.0
In a distributed cache setting broadcasting the control signals out from the single control node to each bank is a physical design issue.
For flush commands, there should be a separate control node per cache bank.
Is there any documentation or block diagram available for the inclusive cache please?
I found that the repo is stand-alone and there is no documentation teaching how to use. So I'm confused. How can I add the cache to rocket-chip?
Hello,I'm reading the code,and don't understand why we should block and nest some request.
and why there are two higher priority MSHR aloneside others?
I'm trying to figure out the clock cycle latency for the L2 inclusive cache - for a hit/miss etc. I can't seem to find it documented anywhere. Can anyone help? Thanks!
There is no lock way design? if no hit, no tagmatch, no bypass, it just picked victimway which is "random" generated by LFSR.
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