taneroksuz/fpu

IEEE 754 floating point library in system-verilog and vhdl

fpu's Issues

32-bit mode only for this great library

Hello,

Thank you for working on this great FPU library for RISC-V.
We are interested in using the library for our 32-bit RISCV softcore.
We noticed that this code is mainly designed to target 64-bit CPUs with 64-bit and 32-bit FPU modes.
Basically, the code converts 32-bit to 64-bit before doing all operations which is costly for our small CPU.
We were wondering how difficult it is to create an optimized version of the library for 32-bit only.
If you could point us to the specific places to make changes, we could do the work and share the change.

thanks.

Compliance Status

Hi,

Could you speak about the compliance status of the FPU? Does it support denormals? Does FMA truncate multiplier's intermediate results? Much appreciated!

How to add this FPU in a design ?

Hi,
I have developed a 32 bits extension of 63/6809 (running at 72 MHz) covered by CeCCIL licence and I'm trying to add a FPU in this CPU. I have found your FPU but I don't understand how I can use it. Do you have a minimal documentation to explain how to add this FPU in a design ? Interface of fp_unit.vhd is very cryptic for me.
Best regards,
JB