ucb-bar/testchipip

testchipip

Useful IP components for chips. BAR projects generally use these components with chipyard.

testchipip.boot

• BootAddrReg: periphery device intended for use with testchipip/bootrom
• TileResetCtrl: memory-mapped Tile-reset registers
• CustomBootPin: I/O for setting non-default boot address to BootAddrReg

testchipip.clocking

• ClockGates, ClockMuxes, ClockDividers, etc.
• ResetSynchronizers

testchipip.cosim

• SpikeCosim: Spike-based cosimulation model
• TraceIO: Utilities for pulling instruction traces out of SoCs
• Dromajo: DEPRECATED Dromajo cosimulation model

testchipip.dram

• SimDRAM: DRAMSim-backed AXI-4 memory model
• SimTLMem: Magic TileLink memory

testchipip.iceblk

• IceBlk: Peripheral block device for FireSim

testchipip.serdes

• GenericSerdesser: Generic Decoupled bidirectional Serdes generators
• TLSerdesser: TileLink bi-directional serializer
• PeripheryTLSerial: Attaches TLSerdesser to chip buses
• SerialWidthAdapter: Converts between serial interfaces of different widths

testchipip.soc

• OffchipBus: Custom bus for interfacing with off-chip memory
• Scratchpad: TileLink SRAM-backed on-chip scratchpad memory
• SimDTM: Simulation model for interacting with on-chip debug module
• TLNetwork: DEPRECATED mechanism for creating a TileLink network-on-chip. Use Constellation NoC instead

testchipip.spi

• SimSPIFlashModel: Simulation model for SPI flash memory

testchipip.tsi

• TSIToTileLink: Converts a TSI master to a TileLink master
• SimTSI: Simulation model for interacting with a TSI interface
• TSIHarness: Utilities for attaching TSI-simulation devices to a TestHarness
• PeripheryUARTTSI: Attaches a TSI-over-UART interface to a bringup FPGA or chip

testchipip.uart

• UARTToSerial: Converts UART to a chip's serial interface
• SimUART: Simulation model for a chip's UART

bootrom/

• Custom BootROM for SoCs with extra bringup features

uart_tsi

• Host utility tool based on FESVR for interfacing with FPGA prototypes or test-chips using the TSI protocol over a UART physical interface

Usage

Testchipip can be used in your project in one of two ways:

1. As an sbt subproject that depends on rocket-chip, as in chipyard
2. As a maven dependency (e.g. write

libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT"

in your build.sbt). Check sonatype to see the latest published version.

testchipip's Issues

Upstream Latency-Injection-Queue

https://github.com/joonho3020/latency-injection-queue/blob/main/src/main/scala/LatencyInjectionQueue.scala

Useful utility

How to use testchipip standalone?

Hi,

is there going to support some unit test or simple example for integrating testchipip such as testchipip.dram?

Best wishes,
Jimmy

How can I used DRAMSIM2?

In chipyard/sims/verilator/ file, I used follow command for simulation in order to test DRAM latency.
./simulator-chipyard-RoCCDMAStrideRocketConfig +verbose ./tests/DMAStrideTest/main.riscv 2>output/RoCCDMAStride
But the memory access latency is similar to SIMAXIMEM , the chapyard version without DRAMSIM2, so how can I used DRAMSIM2 to simulate DRAM? Is the command I used error? @asb @sbeamer @jwright6323 @zhemao @hcook

Incorrect type name in SimDram.cc

I believe lines 64 through 66 in src/main/testchip/csrc/SimDRAM.cc

should be modified as follows

as endianness_t is not defined anywhere.

This fixes an issue when building with building esp-tools and subsequently hwacha in chipyard.

Use PlusArgArtefacts.append to avoid emulator.cc hacks in next RC bump

With this PR (chipsalliance/rocket-chip#2453) we can just add string plusargs or plusargs with no default by calling PlusArgArtefacts.append. This should go in SimUART (to add the uartlog plusarg) and SimSPIFlashModel (there's a comment we can delete explaining what needs to be changed). Additionally you could have multiple logs for multiple UARTs by passing a string parameter to the SimUART verilog module, instead of hardcoding it to uartlog.

SerialAdapter should require minLatency > 0

There is a state machine in the Serial Adapter that seems to assume that d_valid will not be asserted on the same cycle as a_valid when writing. It can't accept the ack on the same cycle that the data is being written. The state machine won't advance if this is the case, even though that is valid Tile Link behavior.

There should be a require(outer.node.minLatency > 0) e.g. here to detect this case, or the state machine should be corrected to handle it:

testchipip/src/main/scala/SerialAdapter.scala

Line 51 in 2797a6c

This is my understanding, the state machine won't accept the write ack (by asserting d_ready) unless it's in write ack state:

testchipip/src/main/scala/SerialAdapter.scala

Line 105 in 2797a6c

mem.d.ready := state.isOneOf(s_write_ack, s_read_data)

But it won't go into write-ack state unless the write is actually accepted:

testchipip/src/main/scala/SerialAdapter.scala

Line 178 in 2797a6c

when (state === s_write_data && mem.a.ready) {

But in tile link it is legal to have a_ready = d_ready.

Is SeqQueue Not Working?

I just replace Queue with SeqQueue, but it doesn't work for me... Is it a wrong usage?

How to use testchipip(DRAMSim2) at chisel-template

Hi, I am studying at chisel3, and want to use the template chisel-template to write an accelerator.
I want to use DRAMSim2 as my DRAM model, and I found out that the testchipip offers a wrapper.
So, I add libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT" in build.sbt as the README.md said.

the build.sbt is

// See README.md for license details.

ThisBuild / scalaVersion     := "2.12.13"
ThisBuild / version          := "0.1.0"
ThisBuild / organization     := "BUS"

lazy val root = (project in file("."))
  .settings(
    name := "xitongzu",
    libraryDependencies ++= Seq(
      "edu.berkeley.cs" %% "chisel3" % "3.4.3",
      "edu.berkeley.cs" %% "chiseltest" % "0.3.3" % "test",
      "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT"
    ),
    scalacOptions ++= Seq(
      "-Xsource:2.11",
      "-language:reflectiveCalls",
      "-deprecation",
      "-feature",
      "-Xcheckinit",
      // Enables autoclonetype2 in 3.4.x (on by default in 3.5)
      "-P:chiselplugin:useBundlePlugin"
    ),
    addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.3" cross CrossVersion.full),
    addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full)
  )

then I import testchipip at src

package MyModules

import chisel3._
import testchipip._

class MyModule extends Module {
    val io = IO(new Bundle {
        val in = Input(UInt(16.W))
        val out = Output(UInt(16.W))
    })

    io.out := RegNext(io.in)
}

but I seem not working. I got the error not found: object testchipip

my repo at chisel-template-mock

Import issue: compile fails, can't find UARTPortIO

Get the following error running sbt console within the root testchipip directory.

[info] Loading project definition from /home/brad/dev/fpga-zynq/testchipip/project
[info] Loading settings for project testchipip from build.sbt ...
[info] Set current project to testchipip (in build file:/home/brad/dev/fpga-zynq/testchipip/)
[info] Compiling 19 Scala sources to /home/brad/dev/fpga-zynq/testchipip/target/scala-2.11/classes ...
[error] /home/brad/dev/fpga-zynq/testchipip/src/main/scala/UARTAdapter.scala:31:28: not found: type UARTPortIO
[error]     val uart = Flipped(new UARTPortIO)
[error]                            ^
[error] one error found
[error] (Compile / compileIncremental) Compilation failed
[error] Total time: 6 s, completed Mar 24, 2020, 3:03:27 PM

Appears related to sifive.blocks.devies.uart._ being out of date, but not sure how to troubleshoot it. Any idea how to correct this?

Bidirectional serdes safe usage

The current code should confirm that no truncation or unsafe padding occurs in the serializers and deserializers.

Support TLSerdesser on separate clock domain.

We may need to clock it slower than the system buses

ClockUtil unit tests

We changed the PeriodMonitor code in #36 but we should probably have unit tests to make sure it doesn't break in the future (on both VCS and verisim).

TSI Host Widget Full Integration Test

Related PR: #113

We should try to have a full integration test where both a host SoC and the test DUT are elaborated, connected, and tested together.

update tile reset control registers for TileResetDomain

I'm trying to use 60d5da8 with rocket that contains chipsalliance/rocket-chip#2641 . That PR changes freechips.rocketchip.tile.TilePRCIDomain so that it no longer has a ClockSinkNode. It has a TileResetDomain that now has the ClockSinkNode.

and I'm running into:

info] Compiling 20 Scala sources to /home/centos/federation_201214/testchipip/target/scala-2.12/classes ...
[error] /home/centos/federation_201214/testchipip/src/main/scala/TileResetCtrl.scala:49:11: value clockSinkNode is not a member of freechips.rocketchip.tile.TilePRCIDomain[_$1]
[error]         d.clockSinkNode.portParams(0).name.get -> r_tile_resets(i).io.q
[error]           ^

I'm starting to look into how to address this but thought I'd file an issue in case @jerryz123, or @hcook or @davidbiancolin already have looked at this.

Eventually move to the `InModuleBody` paradigm instead of `ModuleImp`s to mirror rocket-chip

This is probably out of scope for this PR, but should we eventually move to the InModuleBody paradigm instead of ModuleImps to mirror rocket-chip?

Originally posted by @jwright6323 in #76

Make SimDRAM work when physical address width > 32 bits.

There are lots of assumptions in SimDRAM implementation that addresses are 32-bits wide. These assumptions should be relaxed, we should support multi-GB physical memory.

Provide parameterization of SERIAL_IF_WIDTH

Currently SERIAL_IF_WIDTH is a global constant in https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/SerialAdapter.scala

This should be wrapped into the SerialKey that #58 added to enable configuration at elaboration time

If I want to add an FFT accelerator ,could you give me some tips? Thanks~

SimSerial doesn't handle +permissive

verilator-harness.cc broken due to (my) HTIF/FESVR API changes

My changes to HTIF killed verilator-harness.cc (in addition to SimSerial.cc, but it looks like @zhemao already took care of that) and that's percolated into project-template: ucb-bar/chipyard#25.

Basically, verilator-harness.cc just needs to be modified to pass argc/argv to tsi_t. However, that could benefit from a refactor to be more like emulator.cc and get all the command line arguments out in the open.

If I have time, I'll try and take a look.

value += is not a member of String

Hi,

I've been playing around with chipyard successfully in a previous version (3a83cd0, March 14), but after the update I did two days ago, I get the following errors for running make inside chipyard/sims/verilator:

[error] /home/user/chipyard/generators/testchipip/src/main/scala/Dromajo.scala:25:19: value += is not a member of String
[error]     dromajoParams += "\n\n" + "#define DROMAJO_RESET_VECTOR " + "\"" + "0x" + f"${p(BootROMParams).hang}%X" + "\""
[error]                   ^
[error] /home/user/chipyard/generators/testchipip/src/main/scala/Dromajo.scala:26:19: value += is not a member of String
[error]     dromajoParams += "\n" + "#define DROMAJO_MMIO_START " + "\"" + "0x" + f"${p(BootROMParams).address + p(BootROMParams).size}%X" + "\""
[error]                   ^
[error] /home/user/chipyard/generators/testchipip/src/main/scala/TraceIO.scala:169:37: missing argument list for method apply in object BundleBridgeNexus
[error] Unapplied methods are only converted to functions when a function type is expected.
[error] You can make this conversion explicit by writing `apply _` or `apply(_,_,_,_)(_)` instead of `apply`.
[error]   val traceNexus = BundleBridgeNexus[Vec[TracedInstruction]]
[error]                                     ^
[error] /home/user/chipyard/generators/testchipip/src/main/scala/TraceIO.scala:175:40: missing argument list for method apply in object BundleBridgeNexus
[error] Unapplied methods are only converted to functions when a function type is expected.
[error] You can make this conversion explicit by writing `apply _` or `apply(_,_,_,_)(_)` instead of `apply`.
[error]   val extTraceNexus = BundleBridgeNexus[Vec[ExtendedTracedInstruction]]
[error]                                        ^
[error] four errors found

There seem to be two types of issues here, but somehow I am feeling that both might have the same cause - hence here together. Correct me if I am wrong, though...
I see that @abejgonzalez did all the work in Dromajo.scala and most of work in TraceIO.scala, so I dare mentioning here - kindly forgive me.
Please, do you have any ideas what might be causing this behavior?
Thanks,
Aleksandar

build error

on using this repo along with rocket-chip following errors
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:14: not found: object cde
[error] import cde.{Parameters, Field}
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:17: not found: type Field
[error] case object SerialInterfaceWidth extends Field[Int]
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:20: not found: type Parameters
[error] def apply(p: Parameters) = p.alterPartial({
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:29: not found: type Parameters
[error] class SerialAdapter(implicit p: Parameters) extends TLModule()(p) {
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:30: overloaded method value apply with alternatives:
[error] [T](pname: config.Field[T], site: config.View)T
[error] [T](pname: config.Field[T])T
[error] cannot be applied to (testchipip.SerialInterfaceWidth.type)
[error] val w = p(SerialInterfaceWidth)
and many more like above

on adding following line to build.sbt
libraryDependencies += "edu.berkeley.cs" %% "cde" % "1.0"

the errors are
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:33: could not find implicit value for parameter p: config.Parameters
[error] val mem = new ClientUncachedTileLinkIO
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:37: ambiguous reference to overloaded definition,
[error] both value p in class SerialAdapter of type cde.Parameters
[error] and value p in class TLModule of type => config.Parameters
[error] match argument types (junctions.PAddrBits.type)
[error] val pAddrBits = p(PAddrBits)
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:38: ambiguous reference to overloaded definition,
[error] both value p in class SerialAdapter of type cde.Parameters
[error] and value p in class TLModule of type => config.Parameters
[error] match argument types (rocket.XLen.type)
[error] val xLen = p(XLen)
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:51: inferred type arguments [Int] do not conform to method apply's type parameter bounds [T <: chisel3.Bits]
[error] val (cmd_read :: cmd_write :: Nil) = Enum(2)
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:51: type mismatch;
[error] found : Int(2)
[error] required: T
[error] val (cmd_read :: cmd_write :: Nil) = Enum(2)
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:54: inferred type arguments [Int] do not conform to method apply's type parameter bounds [T <: chisel3.Bits]
[error] s_write_body :: s_write_data :: s_write_ack :: Nil) = Enum(9)
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:54: type mismatch;
[error] found : Int(9)
[error] required: T
[error] s_write_body :: s_write_data :: s_write_ack :: Nil) = Enum(9)
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:55: inferred type arguments [Any] do not conform to method apply's type parameter bounds [T <: chisel3.core.Data]
[error] val state = Reg(init = s_cmd)
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:55: type mismatch;
[error] found : Any
[error] required: T
[error] val state = Reg(init = s_cmd)
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:76: could not find implicit value for parameter p: config.Parameters
[error] val put_acquire = Put(
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:83: could not find implicit value for parameter p: config.Parameters
[error] val get_acquire = Get(
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:29: type mismatch;
[error] found : cde.Parameters
[error] required: config.Parameters
[error] class SerialAdapter(implicit p: Parameters) extends TLModule()(p) {
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:126: type mismatch;
[error] found : Any
[error] required: chisel3.core.UInt
[error] when (cmd === cmd_write) {
[error] ^
[error] /home/kritik/github/ucb-bar/testchipip/src/main/scala/Adapter.scala:129: type mismatch;

and more
i can post the complete error log if needed

TSI Host Widget Documentation

Related PR: #113

In addition to this being integrated into Chipyard, we should have this widget be documented more extensively in the Chipyard docs.

Failed to generate emulator with errors

Hi,
I clone the project-template project and desire to run it.
However, there are errors at build emulator stage.

[error] /RocketPlatform/testchipip/src/main/scala/Generator.scala:16: type mismatch;
[error] found : freechips.rocketchip.util.ParsedInputNames
[error] required: Seq[String]
[error] lazy val config = getConfig(names)
[error] ^
[error] /RocketPlatform/testchipip/src/main/scala/Generator.scala:18: value root is not a member of object freechips.rocketchip.config.Parameters
[error] lazy val params = Parameters.root(world)
[error] ^
[error] two errors found

It seems Generator.scala( in src/main/scala) needs to revise.
I am not sure that does it cause by using the latest rocket-chip version?

Make BlockDevice base address come from Config

testchipip/src/main/scala/BlockDevice.scala

Line 460 in 6decad8

0x10015000, manager.beatBytes))

I'm running into a situation where the address used by BlockDeviceController conflicts with other devices in my system. I'd like to move the BlockDevice to fit in our address map.

Would you guys be open to a PR that made the base address come out of the Config?

Making Host/Target coordination for the TLSerdesser easier

TLSerdesser should emit a configuration file when building a target (chip) which can be read by the host (fpga) when doing bringup to align the Manager and Client TL parameters across the interface.

Remove dependency on sifive-blocks

The dependency on sifive-blocks really makes maintenance painful. The components which depend on sifive blocks should be moved to chipyard directly.

It cannot compatible 128 bit data length

Hi，

I use this module with 128 bits data length. It seems we can use DATA_BITS to set parameter, but there are so many implicit limits such as:
wire [63:0] __w_data;
output longint r_data,

So how can I adjust DATA_BITS correctly, or must give up parameterization?

compilation failed

Hi，

When I do a make CONFIG=GemminiRocketConfig -j in chipyard, got following error, is it a version problem? thanks.

[info] compiling 25 Scala sources to /home/uadmin/chipyard/generators/testchipip/target/scala-2.12/classes ...
[error] /home/uadmin/chipyard/generators/testchipip/src/main/scala/SPIFlash.scala:9:30: object spi is not a member of package sifive.blocks.devices
[error] import sifive.blocks.devices.spi.{PeripherySPIFlashKey}
[error] ^
[error] /home/uadmin/chipyard/generators/testchipip/src/main/scala/SPIFlash.scala:78:15: not found: value PeripherySPIFlashKey
[error] spi.zip(p(PeripherySPIFlashKey)).zipWithIndex.foreach { case ((port, params), i) =>
[error] ^
[error] /home/uadmin/chipyard/generators/testchipip/src/main/scala/SPIFlash.scala:79:56: value fSize is not a member of Any
[error] val spi_mem = Module(new SimSPIFlashModel(params.fSize, i, rdOnly))
[error] ^
[error] /home/uadmin/chipyard/generators/testchipip/src/main/scala/SPIFlash.scala:79:63: type mismatch;
[error] found : Any
[error] required: Int
[error] val spi_mem = Module(new SimSPIFlashModel(params.fSize, i, rdOnly))
[error] ^
[error] /home/uadmin/chipyard/generators/testchipip/src/main/scala/SPIFlash.scala:82:22: value csWidth is not a member of Any
[error] require(params.csWidth == 1, "I don't know what to do with your extra CS bits. Fix me please.")
[error] ^
[error] /home/uadmin/chipyard/generators/testchipip/src/main/scala/UARTAdapter.scala:29:28: not found: type UARTPortIO
[error] val uart = Flipped(new UARTPortIO(UARTParams(address = 0))) // We do not support the four wire variant
[error] ^
[error] /home/uadmin/chipyard/generators/testchipip/src/main/scala/UARTAdapter.scala:29:39: not found: value UARTParams
[error] val uart = Flipped(new UARTPortIO(UARTParams(address = 0))) // We do not support the four wire variant
[error] ^
[error] /home/uadmin/chipyard/generators/testchipip/src/main/scala/UARTAdapter.scala:29:50: not found: value address
[error] val uart = Flipped(new UARTPortIO(UARTParams(address = 0))) // We do not support the four wire variant
[error] ^
[error] /home/uadmin/chipyard/generators/testchipip/src/main/scala/UARTAdapter.scala:123:25: not found: type UARTPortIO
[error] def connect(uart: Seq[UARTPortIO], baudrate: BigInt = 115200)(implicit p: Parameters) {
[error] ^
[error] /home/uadmin/chipyard/generators/testchipip/src/main/scala/UARTAdapter.scala:130:25: not found: type UARTPortIO
[error] def connect(uart: Seq[UARTPortIO], div: Int) {