Sorry to one question.
Built the vivado project for PYNQ-Z2 board by below command successfully:
cd PYNQ_Composable_Pipeline/boards/Pynq-Z2
make project
When I trying change the static ip : ex: colorthresholding_accel to other ip I created, and compiler the project by the Vivado GUI (Generation Bitstream).
I got below error message about the PREQ_HZ doesn't match between xxx and yyy:
![image](https://user-images.githubusercontent.com/5345648/158377732-cf9151ba-a521-47cb-905f-4f7d0614f1ec.png)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_0/rp_axi_lite0(142857132) and /axi_interconnect_0/m22_couplers/auto_cc/M_AXI(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_0/rp_axi_lite1(142857132) and /axi_interconnect_0/m23_couplers/auto_cc/M_AXI(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_1/rp_axi_lite0(142857132) and /axi_interconnect_0/m24_couplers/auto_cc/M_AXI(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_1/rp_axi_lite1(142857132) and /axi_interconnect_0/m25_couplers/auto_cc/M_AXI(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_fork/rp_axi_lite(142857132) and /axi_interconnect_0/m26_couplers/auto_cc/M_AXI(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/dfx_decoupler_pr_join/rp_axi_lite(142857132) and /axi_interconnect_0/m27_couplers/auto_cc/M_AXI(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_0_out0/S_AXIS(1.42857e+08) and /composable/pr_0/stream_out0(142857132)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_0_out1/S_AXIS(1.42857e+08) and /composable/pr_0/stream_out1(142857132)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_1_out0/S_AXIS(1.42857e+08) and /composable/pr_1/stream_out0(142857132)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_1_out1/S_AXIS(1.42857e+08) and /composable/pr_1/stream_out1(142857132)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_join_out0/S_AXIS(1.42857e+08) and /composable/pr_join/stream_out(142857132)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_fork_out0/S_AXIS(1.42857e+08) and /composable/pr_fork/stream_out0(142857132)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/dfx_decouplers/pr_fork_out1/S_AXIS(1.42857e+08) and /composable/pr_fork/stream_out1(142857132)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_0/stream_in0(142857132) and /composable/dfx_decouplers/pr_0_in0/M_AXIS(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_0/stream_in1(142857132) and /composable/dfx_decouplers/pr_0_in1/M_AXIS(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_1/stream_in0(142857132) and /composable/dfx_decouplers/pr_1_in0/M_AXIS(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_1/stream_in1(142857132) and /composable/dfx_decouplers/pr_1_in1/M_AXIS(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_fork/stream_in0(142857132) and /composable/dfx_decouplers/pr_fork_in0/M_AXIS(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_join/stream_in0(142857132) and /composable/dfx_decouplers/pr_join_in0/M_AXIS(1.42857e+08)
[BD 41-237] Bus Interface property FREQ_HZ does not match between /composable/pr_join/stream_in1(142857132) and /composable/dfx_decouplers/pr_join_in1/M_AXIS(1.42857e+08)
[BD 41-238] Port/Pin property FREQ_HZ does not match between /composable/pr_0/clk_142M(142857132) and /ps7_0/FCLK_CLK1(1.42857e+08)
[BD 41-238] Port/Pin property FREQ_HZ does not match between /composable/pr_1/clk_142M(142857132) and /ps7_0/FCLK_CLK1(1.42857e+08)
[BD 41-238] Port/Pin property FREQ_HZ does not match between /composable/pr_join/clk_142M(142857132) and /ps7_0/FCLK_CLK1(1.42857e+08)
[BD 41-238] Port/Pin property FREQ_HZ does not match between /composable/pr_fork/clk_142M(142857132) and /ps7_0/FCLK_CLK1(1.42857e+08)
[BD 41-1031] Hdl Generation failed for the IP Integrator design /home/willychiang/Desktop/PYNQ_Composable_Pipeline/boards/Pynq-Z2/cv_dfx_4_pr/cv_dfx_4_pr.srcs/sources_1/bd/video_cp/video_cp.bd
[Vivado 12-4756] Launch of runs aborted due to earlier errors while preparing sub-designs for run execution.
I'm pretty sure my IP each pins are connected correctly.
Does the composable pipeline vivado project can't be built by the GUI interface, and must use the tcl command?