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Home Page: https://yosyshq.net/yosys/
License: ISC License
Yosys Open SYnthesis Suite
Home Page: https://yosyshq.net/yosys/
License: ISC License
splice command is not working on the following model:
module main(a,b);
input a;
output b;
integer i;
assign i = !a;
assign b = i[0];
assert property (b == !a);
endmodule
after reading the file, I run the following commands
proc; opt; splice;
There is a logic_not cell that has a output of width 32, but it should have output width 1.
cell $logic_not $logic_not$logicnot.v:6$1
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 32
connect \A \a
connect \Y { \i [31:1] $auto$splice.cc:234:run$7 }
end
Another one from afl
module U(b);
input b;
reg N=0.0/0'H0;
endmodule
Yosys 0.5+294 (git sha1 e7c018e, afl-clang 3.5.2-2 -fPIC -Os)
-- Parsing `/tmp/lol2.v' using frontend `verilog' --
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/tmp/lol2.v' to AST representation.
Generating RTLIL representation for module `\U'.
Program received signal SIGSEGV, Segmentation fault.
Yosys::AST::AstNode::asReal (this=<optimized out>, is_signed=<optimized out>)
at frontends/ast/ast.cc:835
835 if (is_negative)
(gdb) back
#0 Yosys::AST::AstNode::asReal (this=<optimized out>,
is_signed=<optimized out>) at frontends/ast/ast.cc:835
#1 0x00000000009c8eb7 in Yosys::AST::AstNode::simplify (this=0x1f95eb0,
const_fold=<optimized out>, at_zero=<optimized out>,
in_lvalue=<optimized out>, stage=<optimized out>,
width_hint=<optimized out>,
sign_hint=<error reading variable: Cannot access memory at address 0x1>,
in_param=<optimized out>) at frontends/ast/simplify.cc:1964
#2 0x000000000098bbf3 in Yosys::AST::AstNode::simplify (this=0x1fa52f0,
const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<optimized out>,
sign_hint=<error reading variable: Cannot access memory at address 0x1>,
in_param=<optimized out>) at frontends/ast/simplify.cc:493
#3 0x000000000098bbf3 in Yosys::AST::AstNode::simplify (this=0x1fa51f0,
const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<optimized out>,
sign_hint=<error reading variable: Cannot access memory at address 0x1>,
in_param=<optimized out>) at frontends/ast/simplify.cc:493
#4 0x000000000098bbf3 in Yosys::AST::AstNode::simplify (this=0x1fa50f0,
const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<optimized out>,
sign_hint=<error reading variable: Cannot access memory at address 0x1>,
in_param=<optimized out>) at frontends/ast/simplify.cc:493
#5 0x000000000098bbf3 in Yosys::AST::AstNode::simplify (this=0x1f96330,
const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<optimized out>,
sign_hint=<error reading variable: Cannot access memory at address 0x1>,
---Type <return> to continue, or q <return> to quit---
in_param=<optimized out>) at frontends/ast/simplify.cc:493
#6 0x0000000000985d36 in Yosys::AST::AstNode::simplify (this=0x1f96330,
const_fold=<optimized out>, at_zero=<optimized out>,
in_lvalue=<optimized out>, stage=<optimized out>,
width_hint=<optimized out>,
sign_hint=<error reading variable: Cannot access memory at address 0x0>,
in_param=<optimized out>) at frontends/ast/simplify.cc:78
#7 0x000000000097b7d5 in Yosys::process_module (ast=0x1f96330,
defer=<optimized out>) at frontends/ast/ast.cc:904
#8 0x000000000097ab4d in Yosys::AST::process (design=0x1f8cec0,
ast=<optimized out>, dump_ast1=<optimized out>, dump_ast2=<optimized out>,
dump_vlog=16, nolatches=32, nomeminit=<optimized out>,
nomem2reg=<optimized out>, mem2reg=<optimized out>, lib=<optimized out>,
noopt=<optimized out>, icells=<optimized out>,
ignore_redef=<optimized out>, defer=<optimized out>,
autowire=<optimized out>) at frontends/ast/ast.cc:1014
#9 0x000000000095ab49 in Yosys::VerilogFrontend::execute (
this=<optimized out>, f=<optimized out>, filename=..., args=...,
design=0x1f8cec0) at frontends/verilog/verilog_frontend.cc:323
#10 0x000000000049fca2 in Yosys::Frontend::execute (
this=0x1f6f3a0 <Yosys::VerilogFrontend>, args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 64, capacity 64, design=0x1f8cec0)
at kernel/register.cc:311
#11 0x00000000004a681d in Yosys::Frontend::frontend_call (design=0x1f8cec0,
f=<optimized out>, filename=..., args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 64, capacity 64) at kernel/register.cc:422
#12 0x00000000004a4b20 in Yosys::Frontend::frontend_call (design=0x1f8cec0,
---Type <return> to continue, or q <return> to quit---
f=0x0, filename=..., command=...) at kernel/register.cc:400
#13 0x000000000070daeb in Yosys::run_frontend (filename=..., command=...,
backend_command=<optimized out>, from_to_label=<optimized out>,
design=<optimized out>) at kernel/yosys.cc:834
#14 0x000000000048c2b3 in main (argc=2, argv=0x7fffffffe368)
at kernel/driver.cc:347
Dears,
the following code seems to create problem with yosys read_verilog command.
I've tried both
read_verilog lshift.v
and
read_verilog -D__ICARUS__ lshift.v
This code has been generated by the PandA framework: panda.dei.polimi.it.
kind regards,
Fabrizio
module lshift_expr_FU(in1, in2, out1);
parameter BITSIZE_in1=1, BITSIZE_in2=1, BITSIZE_out1=1, PRECISION=32;
// IN
input signed [BITSIZE_in1-1:0] in1;
input [BITSIZE_in2-1:0] in2;
// OUT
output signed [BITSIZE_out1-1:0] out1;
`ifndef __ICARUS__
function integer log2;
input integer value;
integer temp_value;
begin
temp_value = value-1;
for (log2=0; temp_value>0; log2=log2+1)
temp_value = temp_value>>1;
end
endfunction
`endif
`ifdef __ICARUS__
parameter arg2_bitsize = $clog2(PRECISION);
`else
parameter arg2_bitsize = log2(PRECISION);
`endif
assign out1 = in1 <<< in2[arg2_bitsize-1:0];
endmodule
I have a very specific bug with splitnets that I can only seem to reproduce with these exact settings:
Running the commands
read_verilog input.v
hierarchy
splitnets -ports
write_verilog output.v
on this file: http://pastebin.com/d00zh74b creates this output that begins
* Generated by Yosys 0.5+284 (git sha1 f40d1b7, gcc 5.2.1-15 -fPIC -Os) */
(* src = "test.v:1" *)
module is28(\X[1] , \X[0] , \X[2] , \X[3] , \X[4] , \X[5] , \X[6] , \X[7] , \X[8] , \X[9] , Y);
(* src = "test_synth.v:3825" *)
wire _03796_;
(* src = "test_synth.v:3826" *)
if I run opt before splitnets or hierarchy it outputs
/* Generated by Yosys 0.5+284 (git sha1 f40d1b7, gcc 5.2.1-15 -fPIC -Os) */
(* src = "test.v:1" *)
module is28(\X[9] , \X[8] , \X[7] , \X[6] , \X[5] , \X[4] , \X[3] , \X[2] , \X[0] , \X[1] , Y);
(* src = "test_synth.v:3825" *)
wire _03796_;
(* src = "test_synth.v:3826" *)
I'm not sure which way the split wires are supposed to be ordered, but both of them have 0 and 1 in the wrong order.
If i save the intermediate result to a file between hierarchy and splitnets, it does not reproduce.
Hi,
I try to parse some verilog code with parameterized module. The default value of some parameters are given by expressions rather than constant values. For example:
// multiply.v
`define WIDTH 16
module multiply (
input [A_WIDTH-1:0] a,
input [B_WIDTH-1:0] b,
output [OUT_WIDTH-1:0] out
);
parameter A_WIDTH = `WIDTH;
parameter B_WIDTH = `WIDTH;
parameter OUT_WIDTH = `WIDTH * 2;
assign out = a * b;
endmodule
If I run
./yosys -p "read_verilog multiply.v"
I get the following error:
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `multiply.v' to AST representation.
Generating RTLIL representation for module `\multiply'.
ERROR: Failed to detect width for parameter \OUT_WIDTH at multiply.v:6!
Would you consider fixing this bug, or do you have any suggestion to bypass this issue?
Thanks!
The output of
write_verilog -attr2comment
is not always a comment. For example I get a line like
/* src = "../folder/*srcfile.v */:3" */
Which has an extra */ in the middle of it.
Another one found with afl-fuzz. (as a side note, I am getting tons of out-of-memory crashes when the verilog tries to create wires with exponentially sized widths and such, but I figure that is intended behavior.)
module a;assign 0'sh0
Yosys 0.5+319 (git sha1 089c1e1, afl-clang 3.5.2-2 -fPIC -Os)
-- Parsing `/tmp/lol2.v' using frontend `verilog' --
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/tmp/lol2.v' to AST representation.
Program received signal SIGSEGV, Segmentation fault.
0x00000000009b8cb8 in Yosys::AST::AstNode::mkconst_bits (v=..., is_signed=<optimized out>) at frontends/ast/ast.cc:703
703 node->integer |= (node->bits.back() == RTLIL::S1) << i;
(gdb) back
#0 0x00000000009b8cb8 in Yosys::AST::AstNode::mkconst_bits (v=..., is_signed=<optimized out>) at frontends/ast/ast.cc:703
#1 0x00000000009a232e in Yosys::VERILOG_FRONTEND::const2ast (code=..., case_type=<optimized out>, warn_z=<optimized out>) at frontends/verilog/const2ast.cc:234
#2 0x00000000009a0cdb in Yosys::VERILOG_FRONTEND::const2ast (code=..., case_type=0 '\000', warn_z=<optimized out>) at frontends/verilog/const2ast.cc:153
#3 0x0000000000952af5 in frontend_verilog_yyparse () at frontends/verilog/verilog_parser.y:1305
#4 0x000000000099ded6 in Yosys::VerilogFrontend::execute (this=<optimized out>, f=<optimized out>, filename=..., args=..., design=0x207c0a0) at frontends/verilog/verilog_frontend.cc:313
#5 0x00000000004a85ae in Yosys::Frontend::execute (this=0x205dc20 <Yosys::VerilogFrontend>, args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 64, capacity 64, design=0x207c0a0) at kernel/register.cc:311
#6 0x00000000004af315 in Yosys::Frontend::frontend_call (design=0x207c0a0, f=<optimized out>, filename=..., args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 64, capacity 64) at kernel/register.cc:422
#7 0x00000000004ad585 in Yosys::Frontend::frontend_call (design=0x207c0a0, f=0x0, filename=..., command=...) at kernel/register.cc:400
#8 0x00000000007341fe in Yosys::run_frontend (filename=..., command=..., backend_command=<optimized out>, from_to_label=<optimized out>, design=<optimized out>) at kernel/yosys.cc:834
#9 0x0000000000493c03 in main (argc=2, argv=0x7fffffffe368) at kernel/driver.cc:347
This works:
task DoSomething;
input [7:0] A;
endtask
This gives a syntax error:
task DoSomething(input [7:0] A);
endtask
The same is the case for functions
I'm trying to synthesize with yosys Verilog code instantiating a standard BRAM template.
Yosys works fine until I've added the BRAM initialization.
The snippet of code creating problems is the following:
initial
begin
$readmemb(INIT_file, memory, 0, n_elements-1);
end
Is there any plan for the support of BRAM initialization?
Cheers,
Fabrizio
If the splitnets -driver command divides a register in to different chunks, then its init attribute is lost.
It would be great to retain this information.
Hey,
I get following error:
| |
| yosys -- Yosys Open SYnthesis Suite |
(....)
| |
\----------------------------------------------------------------------------/
Yosys 0.5+336 (git sha1 e51dcc8, clang 3.4-1ubuntu3 -fPIC -Os)
yosys> read_verilog blah.v
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `blah.v' to AST representation.
ERROR: Parser error in line blah.v:1: syntax error
tfr@tfr-laptop:~/Documents/TestArea/Yosys$ cat blah.v
parameter X = 2;
This is just a minimal example of the problem. The problem occurs when I define a parameter outside of a Verilog module. If inside the module, everything is fine:
yosys> read_verilog blah.v
1. Executing Verilog-2005 frontend.
Parsing Verilog input from 'blah.v' to AST representation.
Generating RTLIL representation for module '\top'.
Successfully finished Verilog frontend.
yosys> exit
End of script. Logfile hash: bd98451c1e
CPU: user 0.00s system 0.00s, MEM: 43.50 MB total, 5.19 MB resident
Yosys 0.5+336 (git sha1 e51dcc8, clang 3.4-1ubuntu3 -fPIC -Os)
Time spent: 100% 2x read_verilog (0 sec)
tfr@tfr-laptop:~/Documents/TestArea/Yosys$ cat blah.v
module top(A);
input[7:0] A;
parameter X = 2;
endmodule // top
On different machines this test fails with different error messages. One example:
cd tests/techmap && bash run-test.sh
Running mem_simple_4x1_runtest.sh..
mem_simple_4x1_synth.v:66: error: syntax error in continuous assignment
mem_simple_4x1_synth.v:67: syntax error
mem_simple_4x1_synth.v:67: error: syntax error in continuous assignment
mem_simple_4x1_synth.v:214: syntax error
mem_simple_4x1_synth.v:214: error: syntax error in continuous assignment
mem_simple_4x1_synth.v:215: syntax error
mem_simple_4x1_synth.v:215: error: syntax error in continuous assignment
mem_simple_4x1_synth.v:216: syntax error
mem_simple_4x1_synth.v:216: error: Operand of unary ! is not a primary expression.
mem_simple_4x1_synth.v:216: error: syntax error in continuous assignment
ERROR
make: *** [test] Error 1
Another example:
cd tests/techmap && bash run-test.sh
Running mem_simple_4x1_runtest.sh..
iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v
iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v
mem_simple_4x1_synth.v:41: syntax error
mem_simple_4x1_synth.v:41: error: invalid module item.
mem_simple_4x1_synth.v:43: syntax error
mem_simple_4x1_synth.v:43: error: invalid module item.
mem_simple_4x1_synth.v:46: syntax error
mem_simple_4x1_synth.v:46: error: invalid module item.
mem_simple_4x1_synth.v:48: syntax error
mem_simple_4x1_synth.v:48: error: invalid module item.
ERROR
make: *** [test] Error 1
The second message (on a Linux box) explicitly mentions that iverilog has been launched, so two questions come up:
In both cases, the lines causing the "syntax error" contain attribute comments with the source line numbers:
62 (* src = "mem_simple_4x1_uut.v:4" *)
63 output [7:0] out;
64 (* src = "mem_simple_4x1_uut.v:3" *)
65 input rst;
66 assign _01_ = counter + (* src = "mem_simple_4x1_uut.v:10" *) 1;
67 assign _02_ = counter == (* src = "mem_simple_4x1_uut.v:10" *) 5'b10011;
68 assign _03_ = rst || (* src = "mem_simple_4x1_uut.v:10" *) _02_;
[...]
214 assign _21_ = 1'b1 && (* src = "mem_simple_4x1_map.v:111" *) _23_;
215 assign _22_ = 1'b1 && (* src = "mem_simple_4x1_map.v:97" *) counter[4];
216 assign _23_ = ! (* src = "mem_simple_4x1_map.v:111" *) counter[4];
and
41 (* src = "mem_simple_4x1_uut.v:3" *)
42 input clk;
43 (* src = "mem_simple_4x1_uut.v:5" *)
44 output [4:0] counter;
45 reg [4:0] counter;
46 (* src = "mem_simple_4x1_uut.v:4" *)
47 output [7:0] out;
48 (* src = "mem_simple_4x1_uut.v:3" *)
49 input rst;
(Obviously the tested files look different. What might cause this? From visual inspection, only the attributes seem different, the "real" code looks similar or equal.)
Not sure where to report this, but I think I found a compiler bug somewhere in the yosys+arachne-pnr+icestorm toolchain, and I don't know how to go about debugging it.
These two verilog sources, which run a simple program from ROM when 'a' is sent to the UART, differing in one line, should be equivalent in their result:
https://github.com/laanwj/yosys-ice-experiments/blob/master/error/ok.v#L126
https://github.com/laanwj/yosys-ice-experiments/blob/master/error/fail.v#L123
The first prints a colorful 'hello', however the second gets ptr
wrong and prints random garbage.
The ROM 'program' is assembled here, with the problematic instruction highlighted: https://github.com/laanwj/yosys-ice-experiments/blob/master/error/build.py#L47
The opcode is 0xC8
, which means both rom_rdb[1]
and rom_rdb[0]
are 1'b0
(=register r0). So as I see it {rom_rdb[1],1'b0}
and .rom_rdb[1:0]
should result in 2b'00
. The first however (in fail.v
) produces a result I cannot explain.
Apologies in advance if this is just a misunderstanding in how verilog is supposed to work ... (but that an alternative formulation like cpuregs[rom_rdb&2'h2]
has the same problem convinced me that something may be wrong)
Hi,
I am trying to use the extract command to extract a subcircuit in my design. However, the reference circuit is parameterized, and the default parameters do not match the ones used in the top design. In such a case, yosys fails to detect the subcircuit. I tried to change the default parameters in the reference design to match the top design, then it worked. I also tried -ignore_parameters option, it did not work. I would like a general solution which can handle different parameter values. Is there a way to do this?
Thanks!
module hadder(a, b, s, c);
input a, b;
output s, c;
assign s = a ^ b;
assign c = a & b;
endmodule
module top(a, b, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
input a, b;
output led_7, led_6, led_5, led_4;
output led_3, led_2, led_1, led_0;
hadder u0 (
a,
b,
led_0,
led_1
);
assign {led_7, led_6, led_5, led_4, led_3, led_2} = 0;
endmodule; // top
Synthesising the above code resulted in:
+ /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/edif2ngd -a synth.edif synth.ngo
Release 14.7 - edif2ngd P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 14.7 edif2ngd P.20131013 (lin64)
INFO:NgdBuild - Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
ERROR:NgdBuild:196 - On or above line 148 in file "synth.edif": Problem parsing
"rename". This likely means that the EDIF netlist was improperly written.
Please contact the vendor of the program that produced this EDIF.
Clifford
I've been experimenting with yosys recently and I really like this tool. I was having some trouble with a foundry model and I tracked down the issue to the handling of positive exponents. Here are two excerpts from my .lib file:
wire_load (NONE) {
capacitance : 0.000000;
resistance : 0.000000e+00;
slope : 1.000000;
fanout_length(1, 1.00);
}
elsewhere in the same file
The issue appears to be that the code in LibertyParer::lexer doesn't check for the '+' character giving a syntax error on:
resistance : 0.000000e+00;
and
cell_leakage_power : 3.420563e+00;
I experimented with adding || c == '+' to the two if statements there and it seems to handle these cases correctly. Here is what I got to work:
if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '.' || c == '+')
Thanks again for creating this excellent tool. I hope to be able to help out in the future.
regards,
Ryan
From my understanding of the documentation, wreduce is supposed to reduce the width of cells and wires. It would expect that after one run (or perhaps a few), the width would be minimal, and wreduce would cease to change the design.
If you try the test code used in the documentation with wreduce
module test(input [3:0] a, b, c, output [7:0] y);
assign y = a + b + c + 1;
endmodule
running wreduce repeatedly does not converge, but rather it enters an infinite loop of "removing top bits" from wires. I originally encountered this bug because it seemed wreduce was not removing unused bits in width 2 wires, or at least was introducing new wires with unused bits.
Tried with both clang 3.3 and 3.5.
clang++ -Wall -Wextra -ggdb -I"/tmp/yosys" -MD -D_YOSYS_ -fPIC -I/usr/local/include -std=c++11 -Os -I/usr/local/include/tcl8.6 -DYOSYS_ENABLE_TCL -c -o kernel/register.o kernel/register.cc
kernel/register.cc:309:31: error: no matching member function for call to
'execute'
frontend_register[args[0]]->execute(stdin, "<stdin>", ar...
~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
/tmp/yosys/kernel/register.h:77:15: note: candidate function not viable: no
known conversion from 'FILE *' (aka '__sFILE *') to 'FILE *&'
(aka '__sFILE *&') for 1st argument
virtual void execute(FILE *&f, std::string filename, std::vector...
^
kernel/register.cc:242:16: note: candidate function not viable: requires 2
arguments, but 4 were provided
void Frontend::execute(std::vector<std::string> args, RTLIL::Design *design)
^
kernel/register.cc:402:30: error: no matching member function for call to
'execute'
backend_register[args[0]]->execute(stdout, "<stdout>", a...
~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
/tmp/yosys/kernel/register.h:93:15: note: candidate function not viable: no
known conversion from 'FILE *' (aka '__sFILE *') to 'FILE *&'
(aka '__sFILE *&') for 1st argument
virtual void execute(FILE *&f, std::string filename, std::vecto...
^
kernel/register.cc:336:15: note: candidate function not viable: requires 2
arguments, but 4 were provided
void Backend::execute(std::vector<std::string> args, RTLIL::Design *design)
^
2 errors generated.
<builtin>: recipe for target 'kernel/register.o' failed
gmake: *** [kernel/register.o] Error 1
Building with:
$ gmake CXX=clang++ TCL_VERSION=tcl8.6 TCL_INCLUDE=/usr/local/include/tcl8.6
Hey,
Here is another inconsistency: Verilator and Vivado allows you to optionally end an begin/end section with a semicolon:
module top(A, clk, rst);
input clk, rst;
output A;
always @(posedge clk, posedge rst) begin
A <= '0';
end; // << like this
endmodule
This causes a syntax error using Yosys and works if the ; is removed.
Probably this is left to the language developer to chose whether ; is a syntax error, so please feel free to dismiss this "bug" if it is tedious to change.
I'm seeing that Yosys will not synthesize when there is a reg in always block. For example: http://www.edaplayground.com/s/4/490
I ran this successfully with vavlog/vaelab, so it seems like the above example should work. The Verilog code was generated by MyHDL.
running yosys -S causes this crash
module a(b);inout b;reg c;assign+0-c=b;endmodule
Yosys 0.5+327 (git sha1 b2544cf, afl-clang 3.5.0-10 -fPIC -Os)
-- Parsing `/tmp/min.v' using frontend `verilog' --
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/tmp/min.v' to AST representation.
Generating RTLIL representation for module `\a'.
Successfully finished Verilog frontend.
-- Running command `synth' --
2. Executing SYNTH pass.
2.1. Executing HIERARCHY pass (managing design hierarchy).
2.2. Executing PROC pass (convert processes to netlists).
2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.2.3. Executing PROC_INIT pass (extract init attributes).
2.2.4. Executing PROC_ARST pass (detect async resets in processes).
2.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
2.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).
2.2.7. Executing PROC_DFF pass (convert process syncs to FFs).
2.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \a..
2.4. Executing CHECK pass (checking for obvious problems).
checking module a..
Warning: Wire a.\c is used but has no driver.
found and reported 1 problems.
2.5. Executing OPT pass (performing simple optimizations).
2.5.1. Executing OPT_CONST pass (perform const folding).
2.5.2. Executing OPT_SHARE pass (detect identical cells).
Finding identical cells in module `\a'.
Removed a total of 0 cells.
2.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizier on module \a..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \a.
Performed a total of 0 changes.
2.5.5. Executing OPT_SHARE pass (detect identical cells).
Finding identical cells in module `\a'.
Removed a total of 0 cells.
2.5.6. Executing OPT_RMDFF pass (remove dff with constant values).
Replaced 0 DFF cells.
2.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \a..
2.5.8. Executing OPT_CONST pass (perform const folding).
2.5.9. Finished OPT passes. (There is nothing left to do.)
2.6. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port A of cell a.$sub$/tmp/min.v:1$1 ($sub).
Program received signal SIGSEGV, Segmentation fault.
(anonymous namespace)::WreduceWorker::run_cell (this=0x7fffffffc630, cell=0x2036300)
at passes/opt/wreduce.cc:208
208 if (info->is_output || GetSize(info->ports) > 1)
(gdb) back
#0 (anonymous namespace)::WreduceWorker::run_cell (this=0x7fffffffc630, cell=0x2036300)
at passes/opt/wreduce.cc:208
#1 0x000000000174a475 in run (this=<optimized out>) at passes/opt/wreduce.cc:275
#2 (anonymous namespace)::WreducePass::execute (this=<optimized out>, args=...,
design=<optimized out>) at passes/opt/wreduce.cc:362
#3 0x00000000004ae8bf in Yosys::Pass::call (design=0x20210a0, args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 32, capacity 32) at kernel/register.cc:227
#4 0x00000000004ace99 in Yosys::Pass::call (design=0x20210a0, command=...) at kernel/register.cc:207
#5 0x0000000001bd0651 in (anonymous namespace)::SynthPass::execute (this=<optimized out>, args=...,
design=0x20210a0) at techlibs/common/synth.cc:185
#6 0x00000000004ae8bf in Yosys::Pass::call (design=0x20210a0, args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 32, capacity 32) at kernel/register.cc:227
#7 0x00000000004ace99 in Yosys::Pass::call (design=0x20210a0, command=...) at kernel/register.cc:207
#8 0x0000000000745b0c in Yosys::run_pass (command=..., design=<optimized out>) at kernel/yosys.cc:849
#9 0x00000000004a0276 in main (argc=<optimized out>, argv=<optimized out>) at kernel/driver.cc:363
I am using yosys to handle some verilog code generated from Vivado HLS. The code has some weird style for FSM, and there is a reg with an initial value. After processing the code, I find there is a $dff cell with constant input, and this constant input is equal to the initial value. So I think the cell should be removed by opt_rmdff, but that is not the case. I dive in the code and see that opt_rmdff will skip the dff with init attribute, regardless of whether or not the initial value is equal to the constant. Is there any reason not to do so? If not, I suggest a simple fix to it as
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 5f52bb8..20966fd 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -122,7 +122,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
goto delete_dff;
}
- if (sig_d.is_fully_const() && !sig_r.size() && !has_init) {
+ if (sig_d.is_fully_const() && !sig_r.size() && (!has_init || (has_init && val_init == sig_d.as_const()))) {
RTLIL::SigSig conn(sig_q, sig_d);
mod->connect(conn);
goto delete_dff;
Hi Clifford,
module hadder(a, b, s, c);
input a, b;
output s, c;
assign s = a ^ b;
assign c = a & b;
endmodule // hadder
module adder(ci, a, b, s, co);
input ci, a, b;
output s, co;
wire u0_sum_out;
wire u0_carry_out;
wire u1_carry_out;
hadder u0 (a, b, u0_sum_out, u0_carry_out);
hadder u1 (ci, u0_sum_out, s, u1_carry_out);
assign co = u0_carry_out | u1_carry_out;
endmodule // adder
/**
* Using our half adder implementation and full-adder, we can chain them together into a
* 4-bit ripple carry adder.
*
**/
module top(sw_0, sw_1, sw_2, sw_3, sw_4, sw_5, sw_6, sw_7, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
input sw_0, sw_1, sw_2, sw_3, sw_4, sw_5, sw_6, sw_7;
output led_7, led_6, led_5, led_4;
output led_3, led_2, led_1, led_0;
wire b0_sum, b0_carry;
wire b1_sum, b1_carry;
wire b2_sum, b2_carry;
wire b3_sum, b3_carry;
hadder b0 (sw_0, sw_4, b0_sum, b0_carry); // Bit 0 is just as half adder, as we have no carry in :)
adder b1 (b0_carry, sw_1, sw_5, b1_sum, b1_carry);
adder b2 (b1_carry, sw_2, sw_6, b2_sum, b2_carry);
adder b3 (b2_carry, sw_3, sw_7, b3_sum, b3_carry);
assign {led_7, led_6, led_5} = 0;
assign {led_4, led_3, led_2, led_1, led_0} = {b3_carry, b3_sum, b2_sum, b1_sum, b0_sum};
endmodule // top
Synthesises perfectly in yosys, but edif2ngd gives me an error:
+ /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/edif2ngd -a synth.edif synth.ngo
Release 14.7 - edif2ngd P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 14.7 edif2ngd P.20131013 (lin64)
INFO:NgdBuild - Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
INFO:NgdBuild:1406 - Converting edif 'integer' property 'INIT' with value '14'
on object '$abc$73$auto$blifparse.cc:119:abc_parse_blif$74.lut2.fpga_lut' to
'hexadecimal' property.
ERROR:NgdBuild:175 - On or above line 75 in file "synth.edif": Reference to an
unknown cell "hadder". This likely means that the EDIF netlist was
improperly written. Please contact the vendor of the program that produced
this EDIF file.
I feel like I should try to fix this myself, but have no idea where to start.
Synopsys tools output cells like "INVX1", etc, which yosys does not recognize as logical operations. What would be the best way to get yosys to understand designs like this? Is there a publicly available gatelib for these cells?
Produces the following error when I run a "make test"
Test: test_intermout_always_ff_6_test -> ERROR!
make: *** [test] Error 1
ABC: yosys-abc: src/proof/ssw/sswSim.c:960: Ssw_SmlReinitialize: Assertion `Aig_ManRegNum(p->pAig) < Aig_ManCiNum(p->pAig)' failed.
ABC: Allocated 0.00 MB to store simulation information.
ABC: Initial simulation of 4 frames with 2 words. Time = 0.00 sec
ABC: Collecting candidate equivalence classes. Time = 0.00 sec
ABC: Aborted (core dumped)
It seams like there's a problem with the verilog "generate" statement and a decrement downto 0.
Have a look at the following example:
module test(
alu_data_d_in,
alu_data_d_out
);
input [7:0]alu_data_d_in;
output[7:0]alu_data_d_out;
wire [7:0]swap_out;
genvar i;
generate
for ( i = 7 ; ( i >= 4 ) ; i = ( i - 1 ) )
begin : swap_h
assign swap_out[i] = alu_data_d_in[( ( i - 4 ) )];
end
endgenerate
generate
//for ( i = 0 ; ( i <4 ) ; i = ( i + 1 ) ) //OK
for ( i = 3 ; ( i >=0 ) ; i = ( i - 1 ) ) //FAIL
begin : swap_l
assign swap_out[i] = alu_data_d_in[(i+4 )];
end
endgenerate
assign alu_data_d_out = swap_out;
endmodule
If I use " for ( i = 3 ; ( i >=0 ) ; i = ( i - 1 ) )" instead of "for ( i = 0 ; ( i <4 ) ; i = ( i + 1 ) )" yosys hangs (100% load on one cpu core) without error message and starts consuming more and more memory.
It seams like there is a problem with the 0, because " for ( i = 7 ; ( i >= 4 ) ; i = ( i - 1 ) )" does work.
Also " for ( i = 3 ; ( i >0 ) ; i = ( i - 1 ) )" runs. (However the result is wrong...)
I would assume the below should be pretty much kept as is no matter what passes I run
module top(inout x);
wire y;
btestmod1 m1(.a(x), .b(y));
btestmod1 m2(.a(x), .b(y));
endmodule
(* blackbox *)
module btestmod1(inout a, inout b);
endmodule
What is wrong with the following verilog code? yosys gives parse error at line 16, assign out = 0;
module counter(out, clk, reset);
parameter WIDTH = 8;
output [WIDTH-1 : 0] out;
input clk, reset;
reg [WIDTH-1 : 0] out;
wire clk, reset;
always @(posedge clk)
out <= out + 1;
always @(reset)
if (reset)
assign out = 0;
else
deassign out;
endmodule // counter
$ yosys -q counter.v
ERROR: Parser error in line counter.v:16: syntax error
However, it compiles and runs just fine with iverilog:
$ iverilog -o my_design counter_tb.v counter.v
mustafa@C3PO:~/verilog$ vvp my_design
At time 0, value = xx (x)
At time 17, value = 00 (0)
At time 35, value = 01 (1)
At time 45, value = 02 (2)
At time 55, value = 03 (3)
At time 57, value = 00 (0)
At time 75, value = 01 (1)
At time 85, value = 02 (2)
At time 95, value = 03 (3)
At time 105, value = 04 (4)
At time 115, value = 05 (5)
At time 125, value = 06 (6)
At time 135, value = 07 (7)
At time 145, value = 08 (8)
At time 155, value = 09 (9)
At time 165, value = 0a (10)
** VVP Stop(0) **
** Flushing output streams.
** Current simulation time is 168 ticks.
gcc -Wall -Wextra -ggdb -I"/home/james/develop/yosys" -MD -D_YOSYS_ - fPIC -stdgnu++0x -march=native -O3 -DNDEBUG -I/usr/include/tcl8.5 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_MINISAT -c -o libs/ezsat/ezminisat.o libs/ezsat/ezminisat.cc
libs/ezsat/ezminisat.cc:29:33: fatal error: minisat/core/Solver.h: No such file or directory
#include "minisat/core/Solver.h"
^
compilation terminated.
make: *** [libs/ezsat/ezminisat.o] Error 1
I assume somethings not checked-in.
Also had problems compiling with clang, but that was not finding <stddef.h> so must be something wrong with my library headers.
mfg
James
It might be nice to have a const operator[] in the dict class, for accessing elements from const dicts.
module hadder(a, b, s, c);
input a, b;
output s, c;
assign s = a ^ b;
assign c = a & b;
endmodule
module top(a, b, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
input a, b;
output led_7, led_6, led_5, led_4;
output led_3, led_2, led_1, led_0;
hadder u0 (
a,
b,
led_0,
led_1
);
assign {led_7, led_6, led_5, led_4, led_3, led_2} = 0;
endmodule; // top
I had trouble parsing this code, and eventually found out that it was the semi-colon on the last line which threw the error.
My emacs verilog mode added the semi-colon automatically so I can only assume that its valid syntax although my quick 5 minute search yielded no examples of this.
I am running a fuzzer on yosys. This is the first segfault I have found. I believe it is caused by the "1'b_ "
module demo_001(y1, y2, y3, y4);
output [7:0] y1, y2, y3, y4;
localparam [7:0] p1 = 123.45;
localparam real p2 = 123.45;
localparam real p3 = 123;
localparam p4 = 123.45;
assign y1 = p1 + 0.2;
assign y2 = p2 + 0.2;
assign y3 = p3 + 0.2;
assign y4 = p4 + 0.2;
endmodule
module demo_002(y0, y1, y2, y3);
output [63:0] y0, y1, y2, y3;
assign y0 = 1'b_ >= (-1 * -1.17);
assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;
assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;
assign y3 = 1 ? -1 : 'd0;
endmodule
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/tmp/lol.v' to AST representation.
Program received signal SIGSEGV, Segmentation fault.
Yosys::my_strtobin (data=..., str=<optimized out>, len_in_bits=1, base=<optimized out>,
case_type=<optimized out>) at frontends/verilog/const2ast.cc:125
125 RTLIL::State msb = data.back();
(gdb) back
#0 Yosys::my_strtobin (data=..., str=<optimized out>, len_in_bits=1, base=<optimized out>,
case_type=<optimized out>) at frontends/verilog/const2ast.cc:125
#1 0x000000000095e456 in Yosys::VERILOG_FRONTEND::const2ast (code=..., case_type=0 '\000',
warn_z=<optimized out>) at frontends/verilog/const2ast.cc:213
#2 0x000000000095d40f in Yosys::VERILOG_FRONTEND::const2ast (code=..., case_type=0 '\000',
warn_z=<optimized out>) at frontends/verilog/const2ast.cc:153
#3 0x0000000000911f6d in frontend_verilog_yyparse () at frontends/verilog/verilog_parser.y:1303
#4 0x000000000095a696 in Yosys::VerilogFrontend::execute (this=<optimized out>, f=<optimized out>,
filename=..., args=..., design=0x1f8cec0) at frontends/verilog/verilog_frontend.cc:313
#5 0x000000000049fca2 in Yosys::Frontend::execute (this=0x1f6f3a0 <Yosys::VerilogFrontend>, args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 64, capacity 64, design=0x1f8cec0) at kernel/register.cc:311
#6 0x00000000004a681d in Yosys::Frontend::frontend_call (design=0x1f8cec0, f=<optimized out>,
filename=..., args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 64, capacity 64) at kernel/register.cc:422
#7 0x00000000004a4b20 in Yosys::Frontend::frontend_call (design=0x1f8cec0, f=0x0, filename=...,
command=...) at kernel/register.cc:400
#8 0x000000000070daeb in Yosys::run_frontend (filename=..., command=...,
backend_command=<optimized out>, from_to_label=<optimized out>, design=<optimized out>)
at kernel/yosys.cc:834
#9 0x000000000048c2b3 in main (argc=2, argv=0x7fffffffe378) at kernel/driver.cc:347
Currently the above fails with an assert:
ERROR: Assert `digits[i] < 10' failed in frontends/verilog/const2ast.cc:51
Another crash found using afl-fuzz
module a(b);
input b;
reg c;
task a(b);
endmodule
-- Parsing `/tmp/lol.v' using frontend `verilog' --
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/tmp/lol.v' to AST representation.
Program received signal SIGSEGV, Segmentation fault.
Yosys::AST::AstNode::operator= (this=0x1f95c10) at frontends/ast/ast.h:145
145 struct AstNode
(gdb) back
#0 Yosys::AST::AstNode::operator= (this=0x1f95c10) at frontends/ast/ast.h:145
#1 0x0000000000966bc6 in Yosys::AST::AstNode::clone (this=0x0) at frontends/ast/ast.cc:217
#2 0x00000000009013c4 in frontend_verilog_yyparse () at frontends/verilog/verilog_parser.y:711
#3 0x000000000095a696 in Yosys::VerilogFrontend::execute (this=<optimized out>, f=<optimized out>, filename=..., args=..., design=0x1f8cec0) at frontends/verilog/verilog_frontend.cc:313
#4 0x000000000049fca2 in Yosys::Frontend::execute (this=0x1f6f3a0 <Yosys::VerilogFrontend>, args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 64, capacity 64, design=0x1f8cec0) at kernel/register.cc:311
#5 0x00000000004a681d in Yosys::Frontend::frontend_call (design=0x1f8cec0, f=<optimized out>, filename=..., args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 64, capacity 64) at kernel/register.cc:422
#6 0x00000000004a4b20 in Yosys::Frontend::frontend_call (design=0x1f8cec0, f=0x0, filename=..., command=...) at kernel/register.cc:400
#7 0x000000000070daeb in Yosys::run_frontend (filename=..., command=..., backend_command=<optimized out>, from_to_label=<optimized out>, design=<optimized out>) at kernel/yosys.cc:834
#8 0x000000000048c2b3 in main (argc=2, argv=0x7fffffffe378) at kernel/driver.cc:347
yosys -S file.v
module a(b);inout b=0==c;assign c=^K;assign c=9^k;integer c#0;endmodule
-- Parsing `/tmp/min.v' using frontend `verilog' --
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/tmp/min.v' to AST representation.
Generating RTLIL representation for module `\a'.
Warning: Identifier `\K' is implicitly declared at /tmp/min.v:1.
Warning: Identifier `\k' is implicitly declared at /tmp/min.v:1.
Successfully finished Verilog frontend.
-- Running command `synth' --
2. Executing SYNTH pass.
2.1. Executing HIERARCHY pass (managing design hierarchy).
2.2. Executing PROC pass (convert processes to netlists).
2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.2.3. Executing PROC_INIT pass (extract init attributes).
2.2.4. Executing PROC_ARST pass (detect async resets in processes).
2.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
2.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).
2.2.7. Executing PROC_DFF pass (convert process syncs to FFs).
2.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \a..
2.4. Executing CHECK pass (checking for obvious problems).
checking module a..
Warning: multiple conflicting drivers for a.\c [31]:
port Y[31] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[31] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [30]:
port Y[30] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[30] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [29]:
port Y[29] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[29] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [28]:
port Y[28] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[28] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [27]:
port Y[27] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[27] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [26]:
port Y[26] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[26] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [25]:
port Y[25] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[25] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [24]:
port Y[24] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[24] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [23]:
port Y[23] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[23] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [22]:
port Y[22] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[22] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [21]:
port Y[21] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[21] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [20]:
port Y[20] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[20] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [19]:
port Y[19] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[19] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [18]:
port Y[18] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[18] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [17]:
port Y[17] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[17] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [16]:
port Y[16] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[16] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [15]:
port Y[15] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[15] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [14]:
port Y[14] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[14] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [13]:
port Y[13] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[13] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [12]:
port Y[12] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[12] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [11]:
port Y[11] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[11] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [10]:
port Y[10] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[10] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [9]:
port Y[9] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[9] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [8]:
port Y[8] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[8] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [7]:
port Y[7] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[7] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [6]:
port Y[6] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[6] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [5]:
port Y[5] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[5] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [4]:
port Y[4] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[4] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [3]:
port Y[3] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[3] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [2]:
port Y[2] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[2] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [1]:
port Y[1] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[1] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: multiple conflicting drivers for a.\c [0]:
port Y[0] of cell $reduce_xor$/tmp/min.v:1$2 ($reduce_xor)
port Y[0] of cell $xor$/tmp/min.v:1$3 ($xor)
Warning: Wire a.\k is used but has no driver.
Warning: Wire a.\K is used but has no driver.
found and reported 34 problems.
2.5. Executing OPT pass (performing simple optimizations).
2.5.1. Executing OPT_CONST pass (perform const folding).
Replacing $eq cell `$eq$/tmp/min.v:1$1' in module `a' with $logic_not.
2.5.2. Executing OPT_SHARE pass (detect identical cells).
Finding identical cells in module `\a'.
Removed a total of 0 cells.
2.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizier on module \a..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \a.
Performed a total of 0 changes.
2.5.5. Executing OPT_SHARE pass (detect identical cells).
Finding identical cells in module `\a'.
Removed a total of 0 cells.
2.5.6. Executing OPT_RMDFF pass (remove dff with constant values).
Replaced 0 DFF cells.
2.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \a..
2.5.8. Executing OPT_CONST pass (perform const folding).
2.5.9. Finished OPT passes. (There is nothing left to do.)
2.6. Executing WREDUCE pass (reducing word size of cells).
Removed top 28 bits (of 32) from port A of cell a.$xor$/tmp/min.v:1$3 ($xor).
Program received signal SIGSEGV, Segmentation fault.
(anonymous namespace)::WreduceWorker::run_cell (this=0x7fffffffc630, cell=0x2038db0)
at passes/opt/wreduce.cc:208
warning: Source file is more recent than executable.
208
(gdb) back
#0 (anonymous namespace)::WreduceWorker::run_cell (this=0x7fffffffc630, cell=0x2038db0)
at passes/opt/wreduce.cc:208
#1 0x000000000174a475 in run (this=<optimized out>) at passes/opt/wreduce.cc:275
#2 (anonymous namespace)::WreducePass::execute (this=<optimized out>, args=...,
design=<optimized out>) at passes/opt/wreduce.cc:362
#3 0x00000000004ae8bf in Yosys::Pass::call (design=0x20210a0, args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 32, capacity 32) at kernel/register.cc:227
#4 0x00000000004ace99 in Yosys::Pass::call (design=0x20210a0, command=...) at kernel/register.cc:207
#5 0x0000000001bd0651 in (anonymous namespace)::SynthPass::execute (this=<optimized out>, args=...,
design=0x20210a0) at techlibs/common/synth.cc:185
#6 0x00000000004ae8bf in Yosys::Pass::call (design=0x20210a0, args=warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
warning: Type size unknown, assuming 1. Try casting to a known type, or void *.
Python Exception <class 'gdb.error'> Cannot perform pointer math on incomplete type "std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >", try casting to a known type, or void *.:
std::vector of length 32, capacity 32) at kernel/register.cc:227
#7 0x00000000004ace99 in Yosys::Pass::call (design=0x20210a0, command=...) at kernel/register.cc:207
#8 0x0000000000745b0c in Yosys::run_pass (command=..., design=<optimized out>) at kernel/yosys.cc:849
#9 0x00000000004a0276 in main (argc=<optimized out>, argv=<optimized out>) at kernel/driver.cc:363
(gdb)
It would be nice to be able to manipulate selections with the same functions that the "select" command uses.
I'm not sure if it would be feasible to integrate such functionality into the RTLIL::Selection class.
I'm trying to write a plugin that requires evaluating combinatorial circuits. From what I can gather ConstEval is the tool which does this. However, the API is not so clear to me. Is there somewhere a rundown of the members of ConstEval and what they do?
verilog :) $ gdb yosys -p 'synth_ice40 -top Raptor64 -blif example.blif' Raptor64*.v
(gdb) run -p 'synth_ice40 -top Raptor64 -blif example.blif' Raptor64*.v
Starting program: /usr/local/bin/yosys -p 'synth_ice40 -top Raptor64 -blif example.blif' Raptor64*.v
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/usr/lib/libthread_db.so.1".
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2015 Clifford Wolf <[email protected]> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.5+249 (git sha1 8d6d5c3, clang 3.6.2 -fPIC -Os)
-- Parsing `Raptor64_addsub.v' using frontend `verilog' --
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64_addsub.v' to AST representation.
Generating RTLIL representation for module `\Raptor64_addsub'.
Note: Assuming pure combinatorial block at Raptor64_addsub.v:45 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.
-- Parsing `Raptor64_bitfield.v' using frontend `verilog' --
2. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64_bitfield.v' to AST representation.
Generating RTLIL representation for module `\Raptor64_bitfield'.
Note: Assuming pure combinatorial block at Raptor64_bitfield.v:54 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Note: Assuming pure combinatorial block at Raptor64_bitfield.v:58 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.
-- Parsing `Raptor64_BranchHistory.v' using frontend `verilog' --
3. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64_BranchHistory.v' to AST representation.
Generating RTLIL representation for module `\Raptor64_BranchHistory'.
Warning: Blocking assignment to memory in line Raptor64_BranchHistory.v:46 is handled like a non-blocking assignment.
Note: Assuming pure combinatorial block at Raptor64_BranchHistory.v:64 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.
-- Parsing `Raptor64_BypassMux.v' using frontend `verilog' --
4. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64_BypassMux.v' to AST representation.
Generating RTLIL representation for module `\Raptor64_BypassMux'.
Note: Assuming pure combinatorial block at Raptor64_BypassMux.v:41 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.
-- Parsing `Raptor64_dcache_ram.v' using frontend `verilog' --
5. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64_dcache_ram.v' to AST representation.
Generating RTLIL representation for module `\Raptor64_dcache_ram'.
Successfully finished Verilog frontend.
-- Parsing `Raptor64_dcache_tagram.v' using frontend `verilog' --
6. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64_dcache_tagram.v' to AST representation.
Generating RTLIL representation for module `\Raptor64_dcache_tagram'.
Successfully finished Verilog frontend.
-- Parsing `Raptor64Div.v' using frontend `verilog' --
7. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64Div.v' to AST representation.
Generating RTLIL representation for module `\Raptor64Div'.
Warning: Ignoring call to system task $display at Raptor64Div.v:84.
Warning: Ignoring call to system task $display at Raptor64Div.v:93.
Warning: Ignoring call to system task $display at Raptor64Div.v:98.
Generating RTLIL representation for module `\Raptor64Div_tb'.
Successfully finished Verilog frontend.
-- Parsing `Raptor64_EvaluateBranch.v' using frontend `verilog' --
8. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64_EvaluateBranch.v' to AST representation.
Generating RTLIL representation for module `\Raptor64_EvaluateBranch'.
Note: Assuming pure combinatorial block at Raptor64_EvaluateBranch.v:56 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.
-- Parsing `Raptor64_icache_ram.v' using frontend `verilog' --
9. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64_icache_ram.v' to AST representation.
Generating RTLIL representation for module `\Raptor64_icache_ram'.
Successfully finished Verilog frontend.
-- Parsing `Raptor64_icache_ram_x32.v' using frontend `verilog' --
10. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64_icache_ram_x32.v' to AST representation.
Generating RTLIL representation for module `\Raptor64_icache_ram_x32'.
Note: Assuming pure combinatorial block at Raptor64_icache_ram_x32.v:101 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.
-- Parsing `Raptor64_logic.v' using frontend `verilog' --
11. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64_logic.v' to AST representation.
Generating RTLIL representation for module `\Raptor64_logic'.
Note: Assuming pure combinatorial block at Raptor64_logic.v:41 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.
-- Parsing `Raptor64mc_tb.v' using frontend `verilog' --
12. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64mc_tb.v' to AST representation.
Generating RTLIL representation for module `\Raptor64mc_tb'.
Note: Assuming pure combinatorial block at Raptor64mc_tb.v:48 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.
-- Parsing `Raptor64mc.v' using frontend `verilog' --
13. Executing Verilog-2005 frontend.
Parsing Verilog input from `Raptor64mc.v' to AST representation.
Generating RTLIL representation for module `\Raptor64mc'.
Warning: Ignoring call to system task $display at Raptor64mc.v:1654.
Warning: Ignoring call to system task $display at Raptor64mc.v:2360.
Warning: Ignoring call to system task $display at Raptor64mc.v:2515.
Warning: Ignoring call to system task $display at insn_dump.v:1.
Warning: Ignoring call to system task $display at insn_dump.v:5.
Warning: Ignoring call to system task $display at insn_dump.v:7.
Warning: Ignoring call to system task $display at insn_dump.v:8.
Warning: Ignoring call to system task $display at insn_dump.v:9.
Warning: Ignoring call to system task $display at insn_dump.v:10.
Warning: Ignoring call to system task $display at insn_dump.v:11.
Warning: Ignoring call to system task $display at insn_dump.v:12.
Warning: Ignoring call to system task $display at insn_dump.v:13.
Warning: Ignoring call to system task $display at insn_dump.v:14.
Warning: Ignoring call to system task $display at insn_dump.v:21.
Warning: Ignoring call to system task $display at insn_dump.v:22.
Warning: Ignoring call to system task $display at insn_dump.v:23.
Warning: Ignoring call to system task $display at insn_dump.v:24.
Warning: Ignoring call to system task $display at insn_dump.v:32.
Warning: Ignoring call to system task $display at insn_dump.v:33.
Warning: Ignoring call to system task $display at insn_dump.v:34.
Warning: Ignoring call to system task $display at insn_dump.v:35.
Warning: Ignoring call to system task $display at insn_dump.v:36.
Warning: Ignoring call to system task $display at insn_dump.v:37.
Warning: Ignoring call to system task $display at insn_dump.v:38.
Warning: Ignoring call to system task $display at insn_dump.v:39.
Warning: Ignoring call to system task $display at insn_dump.v:40.
Warning: Ignoring call to system task $display at insn_dump.v:41.
Warning: Ignoring call to system task $display at insn_dump.v:42.
Warning: Ignoring call to system task $display at insn_dump.v:43.
Warning: Ignoring call to system task $display at insn_dump.v:44.
Warning: Ignoring call to system task $display at insn_dump.v:45.
Warning: Ignoring call to system task $display at insn_dump.v:46.
Warning: Ignoring call to system task $display at insn_dump.v:47.
Warning: Ignoring call to system task $display at insn_dump.v:48.
Warning: Ignoring call to system task $display at insn_dump.v:49.
Warning: Ignoring call to system task $display at insn_dump.v:50.
Warning: Ignoring call to system task $display at insn_dump.v:51.
Warning: Ignoring call to system task $display at insn_dump.v:52.
Warning: Ignoring call to system task $display at insn_dump.v:53.
Warning: Ignoring call to system task $display at insn_dump.v:56.
Warning: Ignoring call to system task $display at insn_dump.v:57.
Warning: Ignoring call to system task $display at insn_dump.v:58.
Warning: Ignoring call to system task $display at insn_dump.v:59.
Warning: Ignoring call to system task $display at insn_dump.v:60.
Warning: Ignoring call to system task $display at insn_dump.v:61.
Warning: Ignoring call to system task $display at insn_dump.v:62.
Warning: Ignoring call to system task $display at insn_dump.v:63.
Warning: Ignoring call to system task $display at insn_dump.v:64.
Warning: Ignoring call to system task $display at insn_dump.v:65.
Warning: Ignoring call to system task $display at insn_dump.v:66.
Warning: Ignoring call to system task $display at insn_dump.v:67.
Warning: Ignoring call to system task $display at insn_dump.v:68.
Warning: Ignoring call to system task $display at insn_dump.v:69.
Warning: Ignoring call to system task $display at insn_dump.v:70.
Warning: Ignoring call to system task $display at insn_dump.v:71.
Warning: Ignoring call to system task $display at insn_dump.v:72.
Warning: Ignoring call to system task $display at insn_dump.v:73.
Warning: Ignoring call to system task $display at insn_dump.v:74.
Warning: Ignoring call to system task $display at insn_dump.v:75.
Warning: Ignoring call to system task $display at insn_dump.v:76.
Warning: Ignoring call to system task $display at insn_dump.v:77.
Warning: Ignoring call to system task $display at insn_dump.v:78.
Warning: Ignoring call to system task $display at insn_dump.v:79.
Warning: Ignoring call to system task $display at insn_dump.v:80.
Warning: Ignoring call to system task $display at insn_dump.v:81.
Warning: Ignoring call to system task $display at insn_dump.v:82.
Warning: Ignoring call to system task $display at insn_dump.v:83.
Warning: Ignoring call to system task $display at insn_dump.v:84.
Warning: Ignoring call to system task $display at insn_dump.v:85.
Warning: Ignoring call to system task $display at insn_dump.v:86.
Warning: Ignoring call to system task $display at insn_dump.v:87.
Warning: Ignoring call to system task $display at insn_dump.v:88.
Warning: Ignoring call to system task $display at Raptor64mc.v:2864.
Warning: Ignoring call to system task $display at Raptor64mc.v:2932.
Warning: Ignoring call to system task $display at Raptor64mc.v:2948.
Warning: Ignoring call to system task $display at Raptor64mc.v:2997.
Warning: Ignoring call to system task $display at Raptor64mc.v:3093.
Warning: Ignoring call to system task $display at Raptor64mc.v:3109.
Warning: Ignoring call to system task $display at Raptor64mc.v:3125.
Warning: Ignoring call to system task $display at Raptor64mc.v:3149.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:555 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:556 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:557 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:558 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:561 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:681 is handled like a non-blocking assignment.
Warning: Blocking assignment to memory in line Raptor64mc.v:982 is handled like a non-blocking assignment.
Program received signal SIGSEGV, Segmentation fault.
Yosys::AST::AstNode::simplify (this=0x12d8740, const_fold=<optimized out>, at_zero=false,
in_lvalue=<optimized out>, stage=<optimized out>, width_hint=<optimized out>,
sign_hint=<optimized out>, in_param=<optimized out>) at frontends/ast/simplify.cc:1277
1277 children[0]->type == AST_RANGE && children[0]->children.size() == 1) {
(gdb) bt
#0 Yosys::AST::AstNode::simplify (this=0x12d8740, const_fold=<optimized out>, at_zero=false,
in_lvalue=<optimized out>, stage=<optimized out>, width_hint=<optimized out>,
sign_hint=<optimized out>, in_param=<optimized out>) at frontends/ast/simplify.cc:1277
#1 0x00000000005622dd in Yosys::AST::AstNode::simplify (this=0x12d8810, const_fold=<optimized out>,
at_zero=false, in_lvalue=false, stage=2, width_hint=-1, sign_hint=true, in_param=<optimized out>)
at frontends/ast/simplify.cc:493
#2 0x00000000005622dd in Yosys::AST::AstNode::simplify (this=0x12d1870, const_fold=<optimized out>,
at_zero=false, in_lvalue=false, stage=2, width_hint=-1, sign_hint=true, in_param=<optimized out>)
at frontends/ast/simplify.cc:493
#3 0x00000000005622dd in Yosys::AST::AstNode::simplify (this=0xba75b0, const_fold=<optimized out>,
at_zero=false, in_lvalue=false, stage=2, width_hint=-1, sign_hint=true, in_param=<optimized out>)
at frontends/ast/simplify.cc:493
#4 0x0000000000561c23 in Yosys::AST::AstNode::simplify (this=0xba75b0, const_fold=<optimized out>,
at_zero=<optimized out>, in_lvalue=<optimized out>, stage=<optimized out>, width_hint=-1,
sign_hint=true, in_param=<optimized out>) at frontends/ast/simplify.cc:161
#5 0x000000000055f0a3 in Yosys::process_module (ast=0xba75b0, defer=<optimized out>)
at frontends/ast/ast.cc:904
#6 0x000000000055edcb in Yosys::AST::process (design=0xb8adf0, ast=<optimized out>,
dump_ast1=<optimized out>, dump_ast2=<optimized out>, dump_vlog=64, nolatches=72,
nomeminit=<optimized out>, nomem2reg=<optimized out>, mem2reg=<optimized out>, lib=<optimized out>,
noopt=<optimized out>, icells=<optimized out>, ignore_redef=<optimized out>, defer=<optimized out>,
autowire=<optimized out>) at frontends/ast/ast.cc:1014
#7 0x0000000000559743 in Yosys::VerilogFrontend::execute (this=<optimized out>, f=<optimized out>,
filename=..., args=..., design=0xb8adf0) at frontends/verilog/verilog_frontend.cc:316
#8 0x00000000004b8fe4 in Yosys::Frontend::execute (this=0xb6d2f0 <Yosys::VerilogFrontend>,
args=std::vector of length 2, capacity 2 = {...}, design=0xb8adf0) at kernel/register.cc:311
#9 0x00000000004b9b97 in Yosys::Frontend::frontend_call (design=0xb8adf0, f=<optimized out>,
filename=..., args=std::vector of length 2, capacity 2 = {...}) at kernel/register.cc:422
#10 0x00000000004b998a in Yosys::Frontend::frontend_call (design=0xb8adf0, f=0x0, filename=...,
command=...) at kernel/register.cc:400
#11 0x0000000000501f01 in Yosys::run_frontend (filename=..., command=...,
backend_command=<optimized out>, from_to_label=<optimized out>, design=<optimized out>)
at kernel/yosys.cc:834
#12 0x00000000004b5daf in main (argc=29, argv=0x7fffffffe508) at kernel/driver.cc:347
(gdb) quit
A debugging session is active.
Inferior 1 [process 8416] will be killed.
Quit anyway? (y or n) y
Hi Clifford,
I am trying to install yosys (latest git clone), and am getting the following error while running 'make test'. Similar errors seen for test/share & test/fsm.
I'm on Centos 6.4 with python version 2.6.6. Are there any python version dependencies? Couldn't find any mention on your website/README, hence the question.
--- begin error message ---
cd tests/realmath && bash run-test.sh
generating tests..
File "generate.py", line 43
with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f):
^
SyntaxError: invalid syntax
make: *** [test] Error 1
--- end error message ---
Thanks & regards,
Bhaskar
Hi,
I'm new to YOSYS, so I'm maybe missing something. I'm on Ubuntu 12.04, and compiled YOSYS with gcc-4.6.
I did a clone today for both YOSYS (commit 9ea2511) and Icarus Verilog (commit 23ad62f3175683777fe30e59d838e5d0ccd2de19) and I'm getting the following error for partsel and asicworld/code_hdl_models_uart. All other tests seems fine (except for BRAM, but that seems to be work in progress).
Note: Make sure that 'iverilog' is an up-to-date git checkout of icarus verilog.
make[1]: *** [code_hdl_models_uart.v] Error 1
make[1]: Leaving directory `/mada/users/rafaeltp/repository/yosys/tests/asicworld'
make: *** [test] Error 2
From the error files I see the error was during techmap (in Executing OPT_CONST pass). The relevant section of the error file is bellow.
ERROR: Found error in internal cell $paramod$constmap:13475f80e44115aa316d405883a5e764dd9db360$paramod$c93dff91361b8229cab066c0b64da176df19eeef\_90_shift_shiftx.$procmux$2259 ($or) at kernel/rtlil.cc:550:
cell $or $procmux$2259
parameter \A_SIGNED 0
parameter \A_WIDTH 32'00000000000000000000000000000
parameter \B_SIGNED 0
parameter \B_WIDTH 32'00000000000000000000000000000
parameter \Y_WIDTH 1
connect \A $3\overflow[0:0]
connect \B $ne$<techmap.v>:153$865_Y
connect \Y $4\overflow[0:0]
end
It is the same for both cases (with a few IDs changed).
I'm not sure if that is a bug in the code, or something wrong with my setup, but I'd appreciate any insight.
Hallo,
I've detected a possible bug (or feature?) in the handling of the synthesis script (-s projekt.ys):
I've added the following comment:
#Myname: added "-purge" to remove unneeded buffers
Now, I get the following error:
15.9. Finished OPT passes. (There is nothing left to do.)
ERROR: No such command: added (type 'help' for a command overview) outputprep failure: No file map9v3_mapped.blif.
Premature exit.
To me it seems like the colon closes the comment...
If I change the comment to
#Myname added "-purge" to remove unneeded buffers
(Notice the missing colon!) Everything works!
I'm using qflow with yosys from this ppa: https://launchpad.net/~saltmakrell/+archive/ubuntu/ppa
PC' /usr/lib64/gcc/x86_64-slackware-linux/4.7.1/../../../../lib64/libreadline.so: undefined reference to
tgetflag'tgetent' /usr/lib64/gcc/x86_64-slackware-linux/4.7.1/../../../../lib64/libreadline.so: undefined reference to
UP'tputs' /usr/lib64/gcc/x86_64-slackware-linux/4.7.1/../../../../lib64/libreadline.so: undefined reference to
tgoto'tgetnum' /usr/lib64/gcc/x86_64-slackware-linux/4.7.1/../../../../lib64/libreadline.so: undefined reference to
BC'/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
Following patch however seems to fix the compilation issue.
diff --git a/Makefile b/Makefile
index a84a787..e56a69e 100644
--- a/Makefile
+++ b/Makefile
@@ -17,7 +17,7 @@ all: top-all
CXXFLAGS = -Wall -Wextra -ggdb -I"$(shell pwd)" -MD -D_YOSYS_ -fPIC
LDFLAGS = -rdynamic
-LDLIBS = -lstdc++ -lreadline -lm -ldl
+LDLIBS = -lstdc++ -lreadline -lm -ldl -lncurses
-include Makefile.conf
@@ -80,7 +80,7 @@ yosys-config: yosys-config.in
chmod +x yosys-config
yosys-svgviewer: libs/svgviewer/.h libs/svgviewer/.cpp
cd libs/svgviewer && qmake-qt4 && make
cd libs/svgviewer && qmake && make
cp libs/svgviewer/svgviewer yosys-svgviewer
abc:
The check pass will say that a wire is undriven
Warning: Wire S4.\out [0] is used but has no driver.
despite the wire being driven by an instantiated module. To verify that it is erroneous, after flattening, the warning goes away.
To replicate, load the following verilog file, run
proc
check
then to compare, do it again and run
proc
flatten
check
and notice the warnings disappear
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module table_lookup (state, p0, p1, p2, p3);
input [31:0] state;
output [31:0] p0, p1, p2, p3;
wire [7:0] b0, b1, b2, b3;
assign {b0, b1, b2, b3} = state;
T
t0 (b0, {p0[23:0], p0[31:24]}),
t1 ( b1, {p1[15:0], p1[31:16]}),
t2 (b2, {p2[7:0], p2[31:8]} ),
t3 (b3, p3);
endmodule
/* substitue four bytes in a word */
module S4 (in, out);
input [31:0] in;
output [31:0] out;
S
S_0 (in[31:24], out[31:24]),
S_1 (in[23:16], out[23:16]),
S_2 (in[15:8], out[15:8] ),
S_3 (in[7:0], out[7:0] );
endmodule
/* S_box, S_box, S_box*(x+1), S_box*x */
module T (in, out);
input [7:0] in;
output [31:0] out;
S
s0 (in, out[31:24]);
assign out[23:16] = out[31:24];
xS
s4 (in, out[7:0]);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
/* S box */
module S (in, out);
input [7:0] in;
output reg [7:0] out;
always @ (*)
case (in)
8'h00: out <= 8'h63;
8'h01: out <= 8'h7c;
8'h02: out <= 8'h77;
8'h03: out <= 8'h7b;
8'h04: out <= 8'hf2;
8'h05: out <= 8'h6b;
8'h06: out <= 8'h6f;
8'h07: out <= 8'hc5;
8'h08: out <= 8'h30;
8'h09: out <= 8'h01;
8'h0a: out <= 8'h67;
8'h0b: out <= 8'h2b;
8'h0c: out <= 8'hfe;
8'h0d: out <= 8'hd7;
8'h0e: out <= 8'hab;
8'h0f: out <= 8'h76;
8'h10: out <= 8'hca;
8'h11: out <= 8'h82;
8'h12: out <= 8'hc9;
8'h13: out <= 8'h7d;
8'h14: out <= 8'hfa;
8'h15: out <= 8'h59;
8'h16: out <= 8'h47;
8'h17: out <= 8'hf0;
8'h18: out <= 8'had;
8'h19: out <= 8'hd4;
8'h1a: out <= 8'ha2;
8'h1b: out <= 8'haf;
8'h1c: out <= 8'h9c;
8'h1d: out <= 8'ha4;
8'h1e: out <= 8'h72;
8'h1f: out <= 8'hc0;
8'h20: out <= 8'hb7;
8'h21: out <= 8'hfd;
8'h22: out <= 8'h93;
8'h23: out <= 8'h26;
8'h24: out <= 8'h36;
8'h25: out <= 8'h3f;
8'h26: out <= 8'hf7;
8'h27: out <= 8'hcc;
8'h28: out <= 8'h34;
8'h29: out <= 8'ha5;
8'h2a: out <= 8'he5;
8'h2b: out <= 8'hf1;
8'h2c: out <= 8'h71;
8'h2d: out <= 8'hd8;
8'h2e: out <= 8'h31;
8'h2f: out <= 8'h15;
8'h30: out <= 8'h04;
8'h31: out <= 8'hc7;
8'h32: out <= 8'h23;
8'h33: out <= 8'hc3;
8'h34: out <= 8'h18;
8'h35: out <= 8'h96;
8'h36: out <= 8'h05;
8'h37: out <= 8'h9a;
8'h38: out <= 8'h07;
8'h39: out <= 8'h12;
8'h3a: out <= 8'h80;
8'h3b: out <= 8'he2;
8'h3c: out <= 8'heb;
8'h3d: out <= 8'h27;
8'h3e: out <= 8'hb2;
8'h3f: out <= 8'h75;
8'h40: out <= 8'h09;
8'h41: out <= 8'h83;
8'h42: out <= 8'h2c;
8'h43: out <= 8'h1a;
8'h44: out <= 8'h1b;
8'h45: out <= 8'h6e;
8'h46: out <= 8'h5a;
8'h47: out <= 8'ha0;
8'h48: out <= 8'h52;
8'h49: out <= 8'h3b;
8'h4a: out <= 8'hd6;
8'h4b: out <= 8'hb3;
8'h4c: out <= 8'h29;
8'h4d: out <= 8'he3;
8'h4e: out <= 8'h2f;
8'h4f: out <= 8'h84;
8'h50: out <= 8'h53;
8'h51: out <= 8'hd1;
8'h52: out <= 8'h00;
8'h53: out <= 8'hed;
8'h54: out <= 8'h20;
8'h55: out <= 8'hfc;
8'h56: out <= 8'hb1;
8'h57: out <= 8'h5b;
8'h58: out <= 8'h6a;
8'h59: out <= 8'hcb;
8'h5a: out <= 8'hbe;
8'h5b: out <= 8'h39;
8'h5c: out <= 8'h4a;
8'h5d: out <= 8'h4c;
8'h5e: out <= 8'h58;
8'h5f: out <= 8'hcf;
8'h60: out <= 8'hd0;
8'h61: out <= 8'hef;
8'h62: out <= 8'haa;
8'h63: out <= 8'hfb;
8'h64: out <= 8'h43;
8'h65: out <= 8'h4d;
8'h66: out <= 8'h33;
8'h67: out <= 8'h85;
8'h68: out <= 8'h45;
8'h69: out <= 8'hf9;
8'h6a: out <= 8'h02;
8'h6b: out <= 8'h7f;
8'h6c: out <= 8'h50;
8'h6d: out <= 8'h3c;
8'h6e: out <= 8'h9f;
8'h6f: out <= 8'ha8;
8'h70: out <= 8'h51;
8'h71: out <= 8'ha3;
8'h72: out <= 8'h40;
8'h73: out <= 8'h8f;
8'h74: out <= 8'h92;
8'h75: out <= 8'h9d;
8'h76: out <= 8'h38;
8'h77: out <= 8'hf5;
8'h78: out <= 8'hbc;
8'h79: out <= 8'hb6;
8'h7a: out <= 8'hda;
8'h7b: out <= 8'h21;
8'h7c: out <= 8'h10;
8'h7d: out <= 8'hff;
8'h7e: out <= 8'hf3;
8'h7f: out <= 8'hd2;
8'h80: out <= 8'hcd;
8'h81: out <= 8'h0c;
8'h82: out <= 8'h13;
8'h83: out <= 8'hec;
8'h84: out <= 8'h5f;
8'h85: out <= 8'h97;
8'h86: out <= 8'h44;
8'h87: out <= 8'h17;
8'h88: out <= 8'hc4;
8'h89: out <= 8'ha7;
8'h8a: out <= 8'h7e;
8'h8b: out <= 8'h3d;
8'h8c: out <= 8'h64;
8'h8d: out <= 8'h5d;
8'h8e: out <= 8'h19;
8'h8f: out <= 8'h73;
8'h90: out <= 8'h60;
8'h91: out <= 8'h81;
8'h92: out <= 8'h4f;
8'h93: out <= 8'hdc;
8'h94: out <= 8'h22;
8'h95: out <= 8'h2a;
8'h96: out <= 8'h90;
8'h97: out <= 8'h88;
8'h98: out <= 8'h46;
8'h99: out <= 8'hee;
8'h9a: out <= 8'hb8;
8'h9b: out <= 8'h14;
8'h9c: out <= 8'hde;
8'h9d: out <= 8'h5e;
8'h9e: out <= 8'h0b;
8'h9f: out <= 8'hdb;
8'ha0: out <= 8'he0;
8'ha1: out <= 8'h32;
8'ha2: out <= 8'h3a;
8'ha3: out <= 8'h0a;
8'ha4: out <= 8'h49;
8'ha5: out <= 8'h06;
8'ha6: out <= 8'h24;
8'ha7: out <= 8'h5c;
8'ha8: out <= 8'hc2;
8'ha9: out <= 8'hd3;
8'haa: out <= 8'hac;
8'hab: out <= 8'h62;
8'hac: out <= 8'h91;
8'had: out <= 8'h95;
8'hae: out <= 8'he4;
8'haf: out <= 8'h79;
8'hb0: out <= 8'he7;
8'hb1: out <= 8'hc8;
8'hb2: out <= 8'h37;
8'hb3: out <= 8'h6d;
8'hb4: out <= 8'h8d;
8'hb5: out <= 8'hd5;
8'hb6: out <= 8'h4e;
8'hb7: out <= 8'ha9;
8'hb8: out <= 8'h6c;
8'hb9: out <= 8'h56;
8'hba: out <= 8'hf4;
8'hbb: out <= 8'hea;
8'hbc: out <= 8'h65;
8'hbd: out <= 8'h7a;
8'hbe: out <= 8'hae;
8'hbf: out <= 8'h08;
8'hc0: out <= 8'hba;
8'hc1: out <= 8'h78;
8'hc2: out <= 8'h25;
8'hc3: out <= 8'h2e;
8'hc4: out <= 8'h1c;
8'hc5: out <= 8'ha6;
8'hc6: out <= 8'hb4;
8'hc7: out <= 8'hc6;
8'hc8: out <= 8'he8;
8'hc9: out <= 8'hdd;
8'hca: out <= 8'h74;
8'hcb: out <= 8'h1f;
8'hcc: out <= 8'h4b;
8'hcd: out <= 8'hbd;
8'hce: out <= 8'h8b;
8'hcf: out <= 8'h8a;
8'hd0: out <= 8'h70;
8'hd1: out <= 8'h3e;
8'hd2: out <= 8'hb5;
8'hd3: out <= 8'h66;
8'hd4: out <= 8'h48;
8'hd5: out <= 8'h03;
8'hd6: out <= 8'hf6;
8'hd7: out <= 8'h0e;
8'hd8: out <= 8'h61;
8'hd9: out <= 8'h35;
8'hda: out <= 8'h57;
8'hdb: out <= 8'hb9;
8'hdc: out <= 8'h86;
8'hdd: out <= 8'hc1;
8'hde: out <= 8'h1d;
8'hdf: out <= 8'h9e;
8'he0: out <= 8'he1;
8'he1: out <= 8'hf8;
8'he2: out <= 8'h98;
8'he3: out <= 8'h11;
8'he4: out <= 8'h69;
8'he5: out <= 8'hd9;
8'he6: out <= 8'h8e;
8'he7: out <= 8'h94;
8'he8: out <= 8'h9b;
8'he9: out <= 8'h1e;
8'hea: out <= 8'h87;
8'heb: out <= 8'he9;
8'hec: out <= 8'hce;
8'hed: out <= 8'h55;
8'hee: out <= 8'h28;
8'hef: out <= 8'hdf;
8'hf0: out <= 8'h8c;
8'hf1: out <= 8'ha1;
8'hf2: out <= 8'h89;
8'hf3: out <= 8'h0d;
8'hf4: out <= 8'hbf;
8'hf5: out <= 8'he6;
8'hf6: out <= 8'h42;
8'hf7: out <= 8'h68;
8'hf8: out <= 8'h41;
8'hf9: out <= 8'h99;
8'hfa: out <= 8'h2d;
8'hfb: out <= 8'h0f;
8'hfc: out <= 8'hb0;
8'hfd: out <= 8'h54;
8'hfe: out <= 8'hbb;
8'hff: out <= 8'h16;
endcase
endmodule
/* S box * x */
module xS (in, out);
input [7:0] in;
output reg [7:0] out;
always @ (*)
case (in)
8'h00: out <= 8'hc6;
8'h01: out <= 8'hf8;
8'h02: out <= 8'hee;
8'h03: out <= 8'hf6;
8'h04: out <= 8'hff;
8'h05: out <= 8'hd6;
8'h06: out <= 8'hde;
8'h07: out <= 8'h91;
8'h08: out <= 8'h60;
8'h09: out <= 8'h02;
8'h0a: out <= 8'hce;
8'h0b: out <= 8'h56;
8'h0c: out <= 8'he7;
8'h0d: out <= 8'hb5;
8'h0e: out <= 8'h4d;
8'h0f: out <= 8'hec;
8'h10: out <= 8'h8f;
8'h11: out <= 8'h1f;
8'h12: out <= 8'h89;
8'h13: out <= 8'hfa;
8'h14: out <= 8'hef;
8'h15: out <= 8'hb2;
8'h16: out <= 8'h8e;
8'h17: out <= 8'hfb;
8'h18: out <= 8'h41;
8'h19: out <= 8'hb3;
8'h1a: out <= 8'h5f;
8'h1b: out <= 8'h45;
8'h1c: out <= 8'h23;
8'h1d: out <= 8'h53;
8'h1e: out <= 8'he4;
8'h1f: out <= 8'h9b;
8'h20: out <= 8'h75;
8'h21: out <= 8'he1;
8'h22: out <= 8'h3d;
8'h23: out <= 8'h4c;
8'h24: out <= 8'h6c;
8'h25: out <= 8'h7e;
8'h26: out <= 8'hf5;
8'h27: out <= 8'h83;
8'h28: out <= 8'h68;
8'h29: out <= 8'h51;
8'h2a: out <= 8'hd1;
8'h2b: out <= 8'hf9;
8'h2c: out <= 8'he2;
8'h2d: out <= 8'hab;
8'h2e: out <= 8'h62;
8'h2f: out <= 8'h2a;
8'h30: out <= 8'h08;
8'h31: out <= 8'h95;
8'h32: out <= 8'h46;
8'h33: out <= 8'h9d;
8'h34: out <= 8'h30;
8'h35: out <= 8'h37;
8'h36: out <= 8'h0a;
8'h37: out <= 8'h2f;
8'h38: out <= 8'h0e;
8'h39: out <= 8'h24;
8'h3a: out <= 8'h1b;
8'h3b: out <= 8'hdf;
8'h3c: out <= 8'hcd;
8'h3d: out <= 8'h4e;
8'h3e: out <= 8'h7f;
8'h3f: out <= 8'hea;
8'h40: out <= 8'h12;
8'h41: out <= 8'h1d;
8'h42: out <= 8'h58;
8'h43: out <= 8'h34;
8'h44: out <= 8'h36;
8'h45: out <= 8'hdc;
8'h46: out <= 8'hb4;
8'h47: out <= 8'h5b;
8'h48: out <= 8'ha4;
8'h49: out <= 8'h76;
8'h4a: out <= 8'hb7;
8'h4b: out <= 8'h7d;
8'h4c: out <= 8'h52;
8'h4d: out <= 8'hdd;
8'h4e: out <= 8'h5e;
8'h4f: out <= 8'h13;
8'h50: out <= 8'ha6;
8'h51: out <= 8'hb9;
8'h52: out <= 8'h00;
8'h53: out <= 8'hc1;
8'h54: out <= 8'h40;
8'h55: out <= 8'he3;
8'h56: out <= 8'h79;
8'h57: out <= 8'hb6;
8'h58: out <= 8'hd4;
8'h59: out <= 8'h8d;
8'h5a: out <= 8'h67;
8'h5b: out <= 8'h72;
8'h5c: out <= 8'h94;
8'h5d: out <= 8'h98;
8'h5e: out <= 8'hb0;
8'h5f: out <= 8'h85;
8'h60: out <= 8'hbb;
8'h61: out <= 8'hc5;
8'h62: out <= 8'h4f;
8'h63: out <= 8'hed;
8'h64: out <= 8'h86;
8'h65: out <= 8'h9a;
8'h66: out <= 8'h66;
8'h67: out <= 8'h11;
8'h68: out <= 8'h8a;
8'h69: out <= 8'he9;
8'h6a: out <= 8'h04;
8'h6b: out <= 8'hfe;
8'h6c: out <= 8'ha0;
8'h6d: out <= 8'h78;
8'h6e: out <= 8'h25;
8'h6f: out <= 8'h4b;
8'h70: out <= 8'ha2;
8'h71: out <= 8'h5d;
8'h72: out <= 8'h80;
8'h73: out <= 8'h05;
8'h74: out <= 8'h3f;
8'h75: out <= 8'h21;
8'h76: out <= 8'h70;
8'h77: out <= 8'hf1;
8'h78: out <= 8'h63;
8'h79: out <= 8'h77;
8'h7a: out <= 8'haf;
8'h7b: out <= 8'h42;
8'h7c: out <= 8'h20;
8'h7d: out <= 8'he5;
8'h7e: out <= 8'hfd;
8'h7f: out <= 8'hbf;
8'h80: out <= 8'h81;
8'h81: out <= 8'h18;
8'h82: out <= 8'h26;
8'h83: out <= 8'hc3;
8'h84: out <= 8'hbe;
8'h85: out <= 8'h35;
8'h86: out <= 8'h88;
8'h87: out <= 8'h2e;
8'h88: out <= 8'h93;
8'h89: out <= 8'h55;
8'h8a: out <= 8'hfc;
8'h8b: out <= 8'h7a;
8'h8c: out <= 8'hc8;
8'h8d: out <= 8'hba;
8'h8e: out <= 8'h32;
8'h8f: out <= 8'he6;
8'h90: out <= 8'hc0;
8'h91: out <= 8'h19;
8'h92: out <= 8'h9e;
8'h93: out <= 8'ha3;
8'h94: out <= 8'h44;
8'h95: out <= 8'h54;
8'h96: out <= 8'h3b;
8'h97: out <= 8'h0b;
8'h98: out <= 8'h8c;
8'h99: out <= 8'hc7;
8'h9a: out <= 8'h6b;
8'h9b: out <= 8'h28;
8'h9c: out <= 8'ha7;
8'h9d: out <= 8'hbc;
8'h9e: out <= 8'h16;
8'h9f: out <= 8'had;
8'ha0: out <= 8'hdb;
8'ha1: out <= 8'h64;
8'ha2: out <= 8'h74;
8'ha3: out <= 8'h14;
8'ha4: out <= 8'h92;
8'ha5: out <= 8'h0c;
8'ha6: out <= 8'h48;
8'ha7: out <= 8'hb8;
8'ha8: out <= 8'h9f;
8'ha9: out <= 8'hbd;
8'haa: out <= 8'h43;
8'hab: out <= 8'hc4;
8'hac: out <= 8'h39;
8'had: out <= 8'h31;
8'hae: out <= 8'hd3;
8'haf: out <= 8'hf2;
8'hb0: out <= 8'hd5;
8'hb1: out <= 8'h8b;
8'hb2: out <= 8'h6e;
8'hb3: out <= 8'hda;
8'hb4: out <= 8'h01;
8'hb5: out <= 8'hb1;
8'hb6: out <= 8'h9c;
8'hb7: out <= 8'h49;
8'hb8: out <= 8'hd8;
8'hb9: out <= 8'hac;
8'hba: out <= 8'hf3;
8'hbb: out <= 8'hcf;
8'hbc: out <= 8'hca;
8'hbd: out <= 8'hf4;
8'hbe: out <= 8'h47;
8'hbf: out <= 8'h10;
8'hc0: out <= 8'h6f;
8'hc1: out <= 8'hf0;
8'hc2: out <= 8'h4a;
8'hc3: out <= 8'h5c;
8'hc4: out <= 8'h38;
8'hc5: out <= 8'h57;
8'hc6: out <= 8'h73;
8'hc7: out <= 8'h97;
8'hc8: out <= 8'hcb;
8'hc9: out <= 8'ha1;
8'hca: out <= 8'he8;
8'hcb: out <= 8'h3e;
8'hcc: out <= 8'h96;
8'hcd: out <= 8'h61;
8'hce: out <= 8'h0d;
8'hcf: out <= 8'h0f;
8'hd0: out <= 8'he0;
8'hd1: out <= 8'h7c;
8'hd2: out <= 8'h71;
8'hd3: out <= 8'hcc;
8'hd4: out <= 8'h90;
8'hd5: out <= 8'h06;
8'hd6: out <= 8'hf7;
8'hd7: out <= 8'h1c;
8'hd8: out <= 8'hc2;
8'hd9: out <= 8'h6a;
8'hda: out <= 8'hae;
8'hdb: out <= 8'h69;
8'hdc: out <= 8'h17;
8'hdd: out <= 8'h99;
8'hde: out <= 8'h3a;
8'hdf: out <= 8'h27;
8'he0: out <= 8'hd9;
8'he1: out <= 8'heb;
8'he2: out <= 8'h2b;
8'he3: out <= 8'h22;
8'he4: out <= 8'hd2;
8'he5: out <= 8'ha9;
8'he6: out <= 8'h07;
8'he7: out <= 8'h33;
8'he8: out <= 8'h2d;
8'he9: out <= 8'h3c;
8'hea: out <= 8'h15;
8'heb: out <= 8'hc9;
8'hec: out <= 8'h87;
8'hed: out <= 8'haa;
8'hee: out <= 8'h50;
8'hef: out <= 8'ha5;
8'hf0: out <= 8'h03;
8'hf1: out <= 8'h59;
8'hf2: out <= 8'h09;
8'hf3: out <= 8'h1a;
8'hf4: out <= 8'h65;
8'hf5: out <= 8'hd7;
8'hf6: out <= 8'h84;
8'hf7: out <= 8'hd0;
8'hf8: out <= 8'h82;
8'hf9: out <= 8'h29;
8'hfa: out <= 8'h5a;
8'hfb: out <= 8'h1e;
8'hfc: out <= 8'h7b;
8'hfd: out <= 8'ha8;
8'hfe: out <= 8'h6d;
8'hff: out <= 8'h2c;
endcase
endmodule
I have two performance issues with the memory initialization. I am not sure if there are good and easy solutions, or even it is worth it to improve (while I do think these are moderate size applications), but just want to report these issues to motivate some discussion.
First, the verilog frontend runs really slow if there is an initial
block with a moderate-sized $readmemh
function (e.g., 4096 * 32). I attach an example here
https://github.com/gaomy3832/yosys_tests/blob/master/rom.v
https://github.com/gaomy3832/yosys_tests/blob/master/rom_ram.dat
If I run ./yosys -p "read_verilog rom.v;"
, it takes about 15 min.
CPU: user 875.76s system 0.06s, MEM: 110.15 MB total, 86.50 MB resident
Yosys 0.5+332 (git sha1 ddcfc99, clang 3.4-1ubuntu3 -fPIC -Os)
Time spent: 100% 2x read_verilog (875 sec)
Another issue is a little complex. What I want to do is to techmap the BRAM into my custom 1-bit cells (i.e., split the columns). For example, mapping a 64 * 8 BRAM into eight 64 * 1 BRAMs. If I want to preserve the initial values, I need to extract each column from the INIT
parameter, which I assume is stored in row major format. So I try to use a constant function to do the transpose, see the example code here
https://github.com/gaomy3832/yosys_tests/blob/master/transpose.v
If I run ./yosys -p "read_verilog transpose.v"
, it doesn't finish after 30 min (I have to kill it).
I am not sure if using constant function is the best solution, so please let me know if yosys supports a better way to do the work.
A final note for my environment, I ran these tests on a server-class CPU (Xeon E5-2630) so my system should have enough processing power. I've also disabled tcl, abc, and readline when compiling, but I don't think it has any significant effect.
Detected using AFL. I think this is a stack overflow
module a(b);
input b;
reg c;parameter
signed b=b;
endmodule
-- Parsing `/tmp/lol.v' using frontend `verilog' --
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/tmp/lol.v' to AST representation.
Generating RTLIL representation for module `\a'.
Program received signal SIGSEGV, Segmentation fault.
0x00000000009857cc in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=true, at_zero=false, in_lvalue=false, stage=1, width_hint=-1,
sign_hint=<error reading variable: Cannot access memory at address 0x0>, in_param=<error reading variable: Cannot access memory at address 0x7fffff7feb90>) at frontends/ast/simplify.cc:51
51 {
(gdb) back
#0 0x00000000009857cc in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=true, at_zero=false, in_lvalue=false, stage=1, width_hint=-1,
sign_hint=<error reading variable: Cannot access memory at address 0x0>, in_param=<error reading variable: Cannot access memory at address 0x7fffff7feb90>) at frontends/ast/simplify.cc:51
#1 0x00000000009fec80 in Yosys::AST::AstNode::detectSignWidthWorker (this=0x1f95db0, width_hint=@0x7fffff802b18: -1, sign_hint=@0x7fffff802b17: true, found_real=<optimized out>)
at frontends/ast/genrtlil.cc:571
#2 0x0000000000991887 in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<error reading variable: Cannot access memory at address 0xffffffffffffffff>, sign_hint=<error reading variable: Cannot access memory at address 0x1>, in_param=<optimized out>)
at frontends/ast/simplify.cc:309
#3 0x00000000009fec80 in Yosys::AST::AstNode::detectSignWidthWorker (this=0x1f95db0, width_hint=@0x7fffff804c78: -1, sign_hint=@0x7fffff804c77: true, found_real=<optimized out>)
at frontends/ast/genrtlil.cc:571
#4 0x0000000000991887 in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<error reading variable: Cannot access memory at address 0xffffffffffffffff>, sign_hint=<error reading variable: Cannot access memory at address 0x1>, in_param=<optimized out>)
at frontends/ast/simplify.cc:309
#5 0x00000000009fec80 in Yosys::AST::AstNode::detectSignWidthWorker (this=0x1f95db0, width_hint=@0x7fffff806dd8: -1, sign_hint=@0x7fffff806dd7: true, found_real=<optimized out>)
at frontends/ast/genrtlil.cc:571
#6 0x0000000000991887 in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<error reading variable: Cannot access memory at address 0xffffffffffffffff>, sign_hint=<error reading variable: Cannot access memory at address 0x1>, in_param=<optimized out>)
at frontends/ast/simplify.cc:309
#7 0x00000000009fec80 in Yosys::AST::AstNode::detectSignWidthWorker (this=0x1f95db0, width_hint=@0x7fffff808f38: -1, sign_hint=@0x7fffff808f37: true, found_real=<optimized out>)
at frontends/ast/genrtlil.cc:571
#8 0x0000000000991887 in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<error reading variable: Cannot access memory at address 0xffffffffffffffff>, sign_hint=<error reading variable: Cannot access memory at address 0x1>, in_param=<optimized out>)
at frontends/ast/simplify.cc:309
#9 0x00000000009fec80 in Yosys::AST::AstNode::detectSignWidthWorker (this=0x1f95db0, width_hint=@0x7fffff80b098: -1, sign_hint=@0x7fffff80b097: true, found_real=<optimized out>)
at frontends/ast/genrtlil.cc:571
#10 0x0000000000991887 in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<error reading variable: Cannot access memory at address 0xffffffffffffffff>, sign_hint=<error reading variable: Cannot access memory at address 0x1>, in_param=<optimized out>)
at frontends/ast/simplify.cc:309
#11 0x00000000009fec80 in Yosys::AST::AstNode::detectSignWidthWorker (this=0x1f95db0, width_hint=@0x7fffff80d1f8: -1, sign_hint=@0x7fffff80d1f7: true, found_real=<optimized out>)
at frontends/ast/genrtlil.cc:571
#12 0x0000000000991887 in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<error reading variable: Cannot access memory at address 0xffffffffffffffff>, sign_hint=<error reading variable: Cannot access memory at address 0x1>, in_param=<optimized out>)
at frontends/ast/simplify.cc:309
#13 0x00000000009fec80 in Yosys::AST::AstNode::detectSignWidthWorker (this=0x1f95db0, width_hint=@0x7fffff80f358: -1, sign_hint=@0x7fffff80f357: true, found_real=<optimized out>)
at frontends/ast/genrtlil.cc:571
#14 0x0000000000991887 in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<error reading variable: Cannot access memory at address 0xffffffffffffffff>, sign_hint=<error reading variable: Cannot access memory at address 0x1>, in_param=<optimized out>)
at frontends/ast/simplify.cc:309
#15 0x00000000009fec80 in Yosys::AST::AstNode::detectSignWidthWorker (this=0x1f95db0, width_hint=@0x7fffff8114b8: -1, sign_hint=@0x7fffff8114b7: true, found_real=<optimized out>)
at frontends/ast/genrtlil.cc:571
#16 0x0000000000991887 in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<error reading variable: Cannot access memory at address 0xffffffffffffffff>, sign_hint=<error reading variable: Cannot access memory at address 0x1>, in_param=<optimized out>)
at frontends/ast/simplify.cc:309
#17 0x00000000009fec80 in Yosys::AST::AstNode::detectSignWidthWorker (this=0x1f95db0, width_hint=@0x7fffff813618: -1, sign_hint=@0x7fffff813617: true, found_real=<optimized out>)
at frontends/ast/genrtlil.cc:571
#18 0x0000000000991887 in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<error reading variable: Cannot access memory at address 0xffffffffffffffff>, sign_hint=<error reading variable: Cannot access memory at address 0x1>, in_param=<optimized out>)
at frontends/ast/simplify.cc:309
#19 0x00000000009fec80 in Yosys::AST::AstNode::detectSignWidthWorker (this=0x1f95db0, width_hint=@0x7fffff815778: -1, sign_hint=@0x7fffff815777: true, found_real=<optimized out>)
at frontends/ast/genrtlil.cc:571
#20 0x0000000000991887 in Yosys::AST::AstNode::simplify (this=0x1f95eb0, const_fold=<optimized out>, at_zero=false, in_lvalue=false, stage=1,
width_hint=<error reading variable: Cannot access memory at address 0xffffffffffffffff>, sign_hint=<error reading variable: Cannot access memory at address 0x1>, in_param=<optimized out>)
Hi,
the mux optimizer seems to have a problem with scalability in some designs. Try the somewhat nonsensical test case below to create a mux tree controlled by parallel prefix comparators (should synthesize to a few 100 gates). If BITS is larger than a few bits, the optimizer will spin forever. How is this supposed to scale?
/* Count leading zeroes by independent prefix comparison: works for non-power-of-two sizes: */
module count_leading_zeroes (in, out);
parameter BITS = 4; /* no problem */
/* set parameter BITS = 32 or some BIG_NUMBER and watch the optimizer spinning.... */
localparam OUT_BITS = $clog2(BITS) + 1;
input [BITS-1:0] in;
output reg [OUT_BITS-1:0] out;
generate
genvar i;
for (i=0; i<BITS; i=i+1) begin
always @(*) begin
if (in[BITS-1:BITS-1-i] == { { i { 1'b0 } }, 1'b1 }) begin
out = i;
end
end
end
always @(*) begin
if (in == 0) begin
out = { 1'b1 , { OUT_BITS - 1 { 1'b0 } } };
end
end
endgenerate
endmodule
The freduce command segfaults when there is a loop in combinational logic. I had accidently made a loop in my code which uncovered the segfault. I wouldn't expect freduce to work on these loops, but rather throw an error.
Even simple test cases should reproduce the issue:
module test(input en, output reg y);
always @*
y = en & !y;
endmodule
I find a bug with memory_bram. Not sure if it is a real bug or I just misused something, but here it is:
module ram_block (addr, ce, q, clk);
input clk;
input [9:0] addr;
input ce;
output reg [7:0] q;
reg [7:0] ram[1023:0];
always @(posedge clk)
begin
if (ce)
begin
q <= ram[addr];
end
end
endmodule
If I just run ./yosys -p "read_verilog ram_block.v; synth_xilinx -top ram_block"
, it will segfault during memory_bram pass:
...
...
2.7. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
Processing ram_block.ram:
Properties: ports=1 bits=8192 rports=1 wports=0 dbits=8 abits=10 words=1024
Checking rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1):
Bram geometry: abits=9 dbits=72 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__XILINX_RAMB36_SDP: awaste=0 dwaste=64 bwaste=32768 waste=32768 efficiency=11
Rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1) accepted.
Mapping to bram type $__XILINX_RAMB36_SDP (variant 1):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Segmentation fault
The README says
- The system tasks $finish and $display are supported in initial blocks
in and unconditional context (only if/case statements on parameters
and constant values). The intended use for this is synthesis-time DRC.
However, this simple example with read_verilog
command will fail and generate error as
ERROR: System task `$finish' executed at testbench_finish.v:8.
It doesn't provide me any useful information about why it fails. So what is the expected result for $finish? Is there any fundamental difficulty to handle $finish?
The following:
`timescale 1 ns / 1 ps
`default_nettype none
module top(input clk,
output TXD, // UART TX
input RXD, // UART RX
input resetq,
output LED4, // Center led
);
reg outcount [4:0];
always @(posedge uart0_valid) begin
if (outcount > 0) begin
outcount <= outcount - 1;
end
end
endmodule // top
Results in an segmentation error when compiled (as of commit c475dee)
$ yosys -q -p "synth_ice40 -top top -blif error.blif" error.v
Segmentation fault (core dumped)
0x000000000052d98f in Yosys::AST::AstNode::simplify (this=0xa3cb90, const_fold=true, at_zero=at_zero@entry=false, in_lvalue=<optimized out>,
stage=stage@entry=2, width_hint=-1, sign_hint=false, in_param=false) at frontends/ast/simplify.cc:1277
1277 children[0]->type == AST_RANGE && children[0]->children.size() == 1) {
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