antonblanchard/vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Features

Fast

A 2 cycle 64 bit multiply-adder (64bit * 64bit + 128bit -> 128bit) built with the OpenROAD RTL to GDSII flow and the ASAP7 7nm academic PDK makes timing at 1.85 GHz ¹. It takes up 3600um of area:

A 4 cycle 32 bit multiplier (32bit * 32bit -> 64bit), also using OpenROAD and ASAP7 makes timing at 2.7 GHz ¹. Both cases are likely to improve as OpenROAD improves (including better timing aware global placement and global routing, improvements to the resizer, improvements to clock tree synthesis and the use of LVT cells).

vlsiffra achieves this by using many well established techniques including Booth encoding, Dadda reduction and a choice of fast adders like Kogge-Stone.

For more details about these algorithms, check out this Twitter thread which details the implementation of the multiplier in the Bluegene Q supercomputer.

Configurable

vlsiffra is written in the Amaranth HDL language which allows it to be very configurable, including:

• Configurable number of bits

  Any power of two likely works, although Amaranth does start to slow down when building 64 bit multipliers due to a polynomial time complexity issue when adding signals. An issue has been opened to track this and once fixed larger multipliers should be possible.

• Choice of algorithms

  Various addition algorithms are supported:

  • Brent-Kung (less area, lower performance)
  • Kogge-Stone (more area, higher performance)
  • Han-Carlson (a balance of area and performance)
  • Ripple (lowest area, lowest performance)

• Configurable number of stages

  Configurable number of stages, from purely combinational, to 4 register stages. All configurations are fully pipelined. Trade latency for frequency.

Formally verified

Yosys is used to formally verify the standard cell implementation matches gold behavioural models. Amaranth unit tests and Verilator based tests are also used to further verify the design.

Support for many technologies.

vlsiffra currently supports the SkyWater sky130hd, GlobalFoundries GF180MCU and ASAP7 PDKs and standard cell libraries.

Easy to add support for new technologies

vlsiffra only requires a few standard cells (full and half adders, 2 input xor, 2 input and, inverter as well as a couple of more complicated cells (ao21, ao22, ao33)

Installation

vlsiffra is a python package, so this will install it and any dependencies:

pip3 install git+https://github.com/antonblanchard/vlsiffra

Another option is to install it from a checked out source tree:

pip3 install .

Amaranth requires Yosys. If you don't have a version installed, you can use the amaranth-yosys package:

pip3 install amaranth-yosys

Example usage

Create a GF180MCU 64 bit Kogge-Stone adder:

vlsi-adder --bits=64 --algorithm=koggestone --tech=gf180mcu --output=adder.v

Create an ASAP7 32 bit multiplier, using a Brent-Kung adder:

vlsi-multiplier --bits=32 --algorithm=brentkung --tech=asap7 --output=multiplier.v

Create a sky130hd 2 cycle 64 bit multiply-adder, which was taped out in the OpenPOWER Microwatt core for the Google/Efabless/SkyWater MPW7 shuttle (one for the fixed point multiplier and another for the floating point multiplier):

vlsi-multiplier --bits=64 --multiply-add --algorithm=hancarlson --tech=sky130hd --register-post-ppg --output=multiply_adder_pipelined.v

The two multipliers on the Microwatt MPW7 tape out can be seen on the left side of the die:

Testing

Local testing requires an installation of both yosys and verilator. Run make check. Submitting a pull request will kick off the same set of tests.

Adding a new technology

Using ASAP7 as an example:

• A technology file that contains code to instantiate the standard cells required. Use one of the existing ones as a starting point.

  When creating instances, Amaranth uses the i_* prefix for inputs and the o_* prefix for outputs, ie i_VDD means the instance has an input called VDD. As an example, this instantiates the XOR2x1_ASAP7_75t_R xor cell that has A and B inputs and a Y output.

  Also note that ASAP7 inverts the outputs of the full and half adders, so you will see inverters in this file to undo this. Remove them if your technology has non inverting outputs.

  eg Adding the xor definition:

      def _generate_xor(self, a, b, o):
        xorgate = self._PoweredInstance(
            "XOR2x1_ASAP7_75t_R",
            i_A=a,
            i_B=b,
            o_Y=o
        )

        self.m.submodules += xorgate

• Modify get_tech() to hook the new tech up.

• Verilog behavioural models for the standard cells, used for verification.

• Finally add the new technology to the CI here and here.

Issues

• No support for signed multipliers. Planning to add this.

• No support for carry in or carry out of adders. Planning to add this.

• No support for clock gating yet.

• Formal verification of multipliers is slow, and gets unbearably slow as the multiplier reaches 64 bits. As a result, we formally verify smaller configurations only. We should check if we there are faster equivalence checking methods in Yosys. Another idea might be to verify each output bit in a different Yosys process, parallelising things.

• Adding more optional register stages. Splitting Dadda reduction into two cycles and perhaps final addition into two cycles would improve the multiplier frequency.

• We use OpenROAD for cell placement. We might be able to improve the area of the design by doing manual placement, but it's not clear the effort is worth it. We currently use Yosys to instantiate FFs, so we'd need to do this before attempting manual placement.

• Support for 4:2 compressors (basically 2 full adders). This is what Bluegene Q uses and might help to improve area and frequency a bit. We'd need to create a 4:2 compressor cell since none of the standard cell

Why vlsiffra?

My last attempt to name an Open Source project resulted in the impossible to Google for "Microwatt" OpenPOWER VHDL core. vlsiffra is a portmanteau of VLSI and siffra, the Swedish word for number. Thanks to @ruscur for the idea. Hello to all our Swedish readers.

Footnotes

1. ASAP7 RVT cells, STA at best corner, 50 ps reserved in the first and second cycles for input and output logic/routing outside the macro. ↩ ↩²

vlsiffra's Issues

Verilog incompatibility with Openroad

When I use:
vlsi-multiplier --bits=8
to generate an eight-bit multiplier, and then try to read into OpenRoad for physical design (directly, without going thru yosys), I get a verilog syntax error.

The error is on this line:

  assign \$1  = + (* src = "/usr/local/google/home/schmit/pythonenv/vlsiffra/lib/python3.10/site-packages/vlsiffra/multiplier.py\:175" *) { b_registered, 1'h0 };

I think there are two problems. (1) the leading "+" and (2) the size mismatch between RHS and LHS.

1. I don't know why there is this leading "+". Is this an amaranth problem?
2. I think this is more straightforward: $1 is defined as a 10 bit wire, and b_registered is 8 bits. The concatenation does not produce a ten bit quantity.

I think bug (2) is pretty evident. (from multiplier.py):

    multiplicand = Signal(self._bits + 2)

    # Add a zero in the LSB of the multiplier and multiplicand
    self.m.d.comb += [
        multiplier.eq(Cat(Const(0), self.a_registered, Const(0), Const(0))),
        multiplicand.eq(Cat(Const(0), self.b_registered)),
    ]

I suppose there is a possibility that these two things are related. Maybe the leading + is there because there is a width mismatch?

Investigate radix-8 Booth

In large multi-cycle multipliers, the critical path is in the Dadda reduction stage. Adding radix-8 Booth should remove one gate delay from the Dadda stage, the trade off being more complexity (and delay) in the Booth stage.

Add support for signed multipliers

We only support unsigned multipliers at the moment.

Automatically generate a performance table like Teo does with his adders

As part of his https://github.com/tdene/synth_opt_adders repository @tdene regularly generates a spreadsheet found at https://docs.google.com/spreadsheets/d/1pTGzZo5XYU7iuUryxorfzJwNuE9rM3le5t44wmLohy4/edit#gid=233932313

It makes it easy to see what type of performance, area and power you can expect for his adders.

It is also cool to see the performance and results evolve over time.

Add sphinx documentation and readthedocs generation

Sphinx (https://www.sphinx-doc.org/en/master/) is the used by a large number of the existing Python and open source EDA ecosystem (for example the Amaranth's own documentation uses Sphinx, the Google open source PDK's use it like SKY130 and GF180MCU, the F4PGA documentation -- even the Yosys documentation seems to be converting too) and it would be great to see this used here!

See also Teo's documentation @ https://github.com/tdene/synth_opt_adders/tree/main/docs -- There are also examples are http://cfu-playground.rtfd.io/, https://workshop.fomu.im/en/latest/

Other useful extensions for hardware are;

• https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams
• https://github.com/bavovanachte/sphinx-wavedrom
• https://github.com/SymbiFlow/sphinx-verilog-domain

Should the scripts be called `vlsiffra-adder` instead of `vlsi-adder`

It seems a bit weird that the module called vlsiffra installs a script called vlsi-adder rather than vlsiffra-adder?

Add support for 4:2 compressors

4:2 compressors are logically 2 full adders cascaded. The multiplier in Bluegene Q uses them and it might improve area and frequency a bit.

To make this worth it, we'd need to create 4:2 compressor standard cells since none of the Open Source standard cell libraries contain one.

Get into the OpenROAD regression test suite

It seems like some of the things generated from this would be a good benchmarks to be added into the OpenROAD regression test suite.

Create a Python Jupyter Notebook example with a "Launch on Colab" button

@proppy and @tdene have demonstrated that Python Jupyter Notebooks are a great way to documentate and demonstrate the usage of things like vlsiffra. See https://colab.research.google.com/github/tdene/synth_opt_adders/blob/master/docs/notebooks/intro.ipynb for example.

There are also other examples at https://bit.ly/jupyter-silicon

Once you have that a notebook going it then also becomes trivial to hook it up to Google's Vertex AI black box tuner!

I'm sure that @proppy would be interested in helping.

Multipliers with odd bit widths fail

vlsi-multiplier --bits 9

will fail with:
File ".../vlsiffra-1.0.0-py3.10.egg/vlsiffra/multiplier.py", line 64, in elaborate
File ".../vlsiffra-1.0.0-py3.10.egg/vlsiffra/multiplier.py", line 218, in _gen_partial_products
IndexError: list index out of range

Add a `v0.0` tag so that `git-describe` works

Would you mind adding a v0.0 tag to commit 1f82264 ? That will mean that git-describe command produces useful output.

$ git tag -a v0.0 1f8226443247a1122a7a286ef6989c1e12039a0b -m "First commit."
$ git push origin v0.0

Then you get the following on git describe

v0.0-21-g3a02468

TypeError: expected string or bytes-like object, got 'NoneType'

Currently running make pythontests on my machine fails with the following output;

Running 5 test suites (10 total tests) across 5 processes
EEEEEEEEEE
======================================================================
test_random (tests.test_adder.TestCaseBrentKungRandom.test_random)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/tests/test_adder.py", line 47, in test_random
    with sim.write_vcd("adder_random.vcd"):
  File "/usr/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 329, in write_vcd
    vcd_writer = _VCDWriter(self._fragment,
                 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 94, in __init__
    if re.search(r"[ \t\r\n]", var_name):
       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/re/__init__.py", line 176, in search
    return _compile(pattern, flags).search(string)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: expected string or bytes-like object, got 'NoneType'

======================================================================
test_random (tests.test_adder.TestCaseHanCarlsonRandom.test_random)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/tests/test_adder.py", line 99, in test_random
    with sim.write_vcd("adder_random.vcd"):
  File "/usr/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 329, in write_vcd
    vcd_writer = _VCDWriter(self._fragment,
                 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 94, in __init__
    if re.search(r"[ \t\r\n]", var_name):
       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/re/__init__.py", line 176, in search
    return _compile(pattern, flags).search(string)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: expected string or bytes-like object, got 'NoneType'

======================================================================
test_random (tests.test_adder.TestCaseKoggeStoneRandom.test_random)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/tests/test_adder.py", line 73, in test_random
    with sim.write_vcd("adder_random.vcd"):
  File "/usr/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 329, in write_vcd
    vcd_writer = _VCDWriter(self._fragment,
                 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 94, in __init__
    if re.search(r"[ \t\r\n]", var_name):
       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/re/__init__.py", line 176, in search
    return _compile(pattern, flags).search(string)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: expected string or bytes-like object, got 'NoneType'

======================================================================
test_random (tests.test_adder.TestCaseRippleRandom.test_random)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/tests/test_adder.py", line 125, in test_random
    with sim.write_vcd("adder_random.vcd"):
  File "/usr/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 329, in write_vcd
    vcd_writer = _VCDWriter(self._fragment,
                 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 94, in __init__
    if re.search(r"[ \t\r\n]", var_name):
       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/re/__init__.py", line 176, in search
    return _compile(pattern, flags).search(string)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: expected string or bytes-like object, got 'NoneType'

======================================================================
test_random (tests.test_multiplier.TestCaseRandom23.test_random)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/tests/test_multiplier.py", line 64, in test_random
    with sim.write_vcd("multiplier_random23.vcd"):
  File "/usr/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 329, in write_vcd
    vcd_writer = _VCDWriter(self._fragment,
                 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 94, in __init__
    if re.search(r"[ \t\r\n]", var_name):
       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/re/__init__.py", line 176, in search
    return _compile(pattern, flags).search(string)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: expected string or bytes-like object, got 'NoneType'

======================================================================
test_random (tests.test_multiplier.TestCaseRandom32.test_random)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/tests/test_multiplier.py", line 39, in test_random
    with sim.write_vcd("multiplier_random32.vcd"):
  File "/usr/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 329, in write_vcd
    vcd_writer = _VCDWriter(self._fragment,
                 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 94, in __init__
    if re.search(r"[ \t\r\n]", var_name):
       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/re/__init__.py", line 176, in search
    return _compile(pattern, flags).search(string)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: expected string or bytes-like object, got 'NoneType'

======================================================================
test_exhaustive (tests.test_multiplier_exhaustive.TestCaseExhaustive7.test_exhaustive)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/tests/test_multiplier_exhaustive.py", line 62, in test_exhaustive
    with sim.write_vcd("multiplier_exhaustive7.vcd"):
  File "/usr/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 329, in write_vcd
    vcd_writer = _VCDWriter(self._fragment,
                 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 94, in __init__
    if re.search(r"[ \t\r\n]", var_name):
       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/re/__init__.py", line 176, in search
    return _compile(pattern, flags).search(string)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: expected string or bytes-like object, got 'NoneType'

======================================================================
test_exhaustive (tests.test_multiplier_exhaustive.TestCaseExhaustive8.test_exhaustive)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/tests/test_multiplier_exhaustive.py", line 38, in test_exhaustive
    with sim.write_vcd("multiplier_exhaustive8.vcd"):
  File "/usr/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 329, in write_vcd
    vcd_writer = _VCDWriter(self._fragment,
                 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 94, in __init__
    if re.search(r"[ \t\r\n]", var_name):
       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/re/__init__.py", line 176, in search
    return _compile(pattern, flags).search(string)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: expected string or bytes-like object, got 'NoneType'

======================================================================
test_cases (tests.test_multiplier_specific.TestCaseSpecific.test_cases)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/tests/test_multiplier_specific.py", line 59, in test_cases
    with sim.write_vcd("multiplier_specific.vcd"):
  File "/usr/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 329, in write_vcd
    vcd_writer = _VCDWriter(self._fragment,
                 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 94, in __init__
    if re.search(r"[ \t\r\n]", var_name):
       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/re/__init__.py", line 176, in search
    return _compile(pattern, flags).search(string)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: expected string or bytes-like object, got 'NoneType'

======================================================================
test (tests.test_multiply_adder_pipelined.TestCasePipelined.test)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/tests/test_multiply_adder_pipelined.py", line 51, in test
    with sim.write_vcd("multiply_adder_pipelined.vcd"):
  File "/usr/lib/python3.11/contextlib.py", line 137, in __enter__
    return next(self.gen)
           ^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 329, in write_vcd
    vcd_writer = _VCDWriter(self._fragment,
                 ^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/tansell/github/antonblanchard/vlsiffra-clean/venv/lib/python3.11/site-packages/amaranth/sim/pysim.py", line 94, in __init__
    if re.search(r"[ \t\r\n]", var_name):
       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/usr/lib/python3.11/re/__init__.py", line 176, in search
    return _compile(pattern, flags).search(string)
           ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TypeError: expected string or bytes-like object, got 'NoneType'

----------------------------------------------------------------------
Ran 10 tests in 3.668s

FAILED (errors=10)
make: *** [Makefile:9: pythontests] Error 10

Library versions being installed;

ci/create_venv.sh
Processing /home/tansell/github/antonblanchard/vlsiffra-clean
  Installing build dependencies ... done
  Getting requirements to build wheel ... done
  Preparing metadata (pyproject.toml) ... done
Collecting amaranth (from vlsiffra==1.0.0)
  Using cached amaranth-0.3-py3-none-any.whl (167 kB)
Collecting Jinja2~=2.11 (from amaranth->vlsiffra==1.0.0)
  Using cached Jinja2-2.11.3-py2.py3-none-any.whl (125 kB)
Collecting pyvcd~=0.2.2 (from amaranth->vlsiffra==1.0.0)
  Using cached pyvcd-0.2.4-py2.py3-none-any.whl (17 kB)
Collecting MarkupSafe>=0.23 (from Jinja2~=2.11->amaranth->vlsiffra==1.0.0)
  Using cached MarkupSafe-2.1.3-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl (28 kB)
Building wheels for collected packages: vlsiffra
  Building wheel for vlsiffra (pyproject.toml) ... done
  Created wheel for vlsiffra: filename=vlsiffra-1.0.0-py3-none-any.whl size=22726 sha256=6d3d565e2c9a197d4ab97bf8d4d8ee415ba48be0854c37e6f018b30efeeec3f1
  Stored in directory: /home/tansell/.cache/pip/wheels/4e/fa/93/529e7c46f161ea33ecf9add054830566976516d735d1434da5
Successfully built vlsiffra
Installing collected packages: pyvcd, MarkupSafe, Jinja2, amaranth, vlsiffra
Successfully installed Jinja2-2.11.3 MarkupSafe-2.1.3 amaranth-0.3 pyvcd-0.2.4 vlsiffra-1.0.0
Collecting unittest-parallel
  Using cached unittest_parallel-1.6.1-py3-none-any.whl (8.0 kB)
Collecting coverage>=5.1 (from unittest-parallel)
  Using cached coverage-7.3.0-cp311-cp311-manylinux_2_5_x86_64.manylinux1_x86_64.manylinux_2_17_x86_64.manylinux2014_x86_64.whl (232 kB)
Installing collected packages: coverage, unittest-parallel
Successfully installed coverage-7.3.0 unittest-parallel-1.6.1
Collecting flake8
  Using cached flake8-6.1.0-py2.py3-none-any.whl (58 kB)
Collecting mccabe<0.8.0,>=0.7.0 (from flake8)
  Using cached mccabe-0.7.0-py2.py3-none-any.whl (7.3 kB)
Collecting pycodestyle<2.12.0,>=2.11.0 (from flake8)
  Using cached pycodestyle-2.11.0-py2.py3-none-any.whl (31 kB)
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Cleanup old branches?

This repository has a bunch of branches that have been removed and should probably be cleaned up;

• README-updates
• naming
• no-register-const
• better-logo

Make better use of inverting output adders

Some adder cells have inverting outputs (eg ASAP7). At the moment we add inverters to all outputs (S/COUT) but we should be able to avoid them in some cases.

One example is to alternate between adding inverters to the AB inputs and S outputs of chains of full adders, which avoids any inverters on the carry chain. This works because inverting all inputs of a full adder also inverts all of its outputs.

Add clock gating

Adding clock gating would reduce our power consumption, but it's not clear to me how we would add it in Amaranth.

Add carry in/carry out to adder

Most users of the adder will likely need carry in/carry out.