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verilog-arbiter's Issues

Question about arbiter.v and verilator

The issue is Verilator is tossing a warning:
/arbiter.v:60:25: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits.
: ... In instance quadsoc_sim.UUT.wb.wb_arbiter_ram.arbiter0
60 | ff1 = i;
| ^
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)

What the issue is:
function [$clog2(NUM_PORTS)-1:0] ff1;
input [NUM_PORTS-1:0] in;
integer i;
begin

        ff1 = 0;
        for (i = NUM_PORTS-1; i >= 0; i=i-1) begin
            if (in[i])
                ff1 = i; <-- i is an integer and verilator 

        end
    end
endfunction

one way is to add a /* verilator lint_off WIDTH */ is there a better way?

Verilator warnings

Hi,

I'm receiving these warnings while using Verilator to process your core:

%Warning-LITENDIAN: /home/bluecmd/mexiko/rtl/wb_axi/verilog-arbiter/src/arbiter.v:32: Little bit endian vector: MSB < LSB of bit range: 0:1
%Warning-LITENDIAN: Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
%Warning-LITENDIAN: /home/bluecmd/mexiko/rtl/wb_axi/verilog-arbiter/src/arbiter.v:33: Little bit endian vector: MSB < LSB of bit range: 0:1

%Warning-WIDTH: /home/bluecmd/mexiko/rtl/wb_axi/verilog-arbiter/src/arbiter.v:92: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REPLICATE generates 4 bits.
%Warning-WIDTH: /home/bluecmd/mexiko/rtl/wb_axi/verilog-arbiter/src/arbiter.v:92: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REPLICATE generates 3 bits.

For the first 3 lines the fix I guess is just to add

/* verilator lint_off LITENDIAN */ 

and

/* verilator lint_on LITENDIAN */

Changing the declaration of the module would probably be infeasible.

For the width I'm not sure what the fix would be. To me the lines look strange but it's probably my Verilog knowledge that is lacking.

If you could fix these warnings I would be very thankful.

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