cepdnaclk/e16-co502-rv32im-pipeline-implementation-group1

The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.

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RV32IM pipeline implementation

RV32IM pipeline implementation

How to run a simple program in pipeline CPU

1. Add the assembly program to code /cpu directory.

2. Run the script test-program.sh with the program file as the arguemnt ./test-program.sh program.s

   Now cpu_pipeline_wavedata.vcd will be created in /cpu/cpu_pipeline directory.

3. Open cpu_pipeline_wavedata.vcd with gtkwave to observe the signal changes.

IMPORTANT!

iverilog version 11 is required, Lower version of iverilog other than 11 will cause unexpected outputs.