pnnl/opencgra

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

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OpenCGRA is a parameterizable and powerful CGRA (Coarse-Grained Reconfigurable Arrays) generator to generate synthesizable Verilog for different CGRAs based on user-specified configurations (e.g., CGRA size, type of the computing units in each tile, communication connection, etc.). OpenCGRA uses modular design and standardized interfaces between modules. The configurability and extensibility are maximized by its parametrization system to fit in various research and industrial needs.

Docker

The docker image is available here.

Related publications

• Cheng Tan, et al. “AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators.” The 2021 Design, Automation & Test in Europe Conference, Grenoble, France. (DATE-21) February 1-5, 2021.
• Cheng Tan, et al. "ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing." IEEE Transactions on Parallel and Distributed Systems (TPDS-21).
• Cheng Tan, et al. "OpenCGRA: An Open-Source Framework for Modeling, Testing, and Evaluating CGRAs." The 38th IEEE International Conference on Computer Design. (ICCD-20), Oct 2020.

License

OpenCGRA is offered under the terms of the Open Source Initiative BSD 3-Clause License. More information about this license can be found here:

• http://choosealicense.com/licenses/bsd-3-clause
• http://opensource.org/licenses/BSD-3-Clause

Installation

OpenCGRA requires Python3.7 (note that <2.x and >3.7 do not work for now) and has the following additional prerequisites:

• graphviz, verilator
• git, Python headers, and libffi
• virtualenv
• PyMTL3

The steps for installing these prerequisites and OpenCGRA on a fresh Ubuntu distribution are shown below. They have been tested with Ubuntu Trusty 14.04 ~ 20.04.

Install python3

 % sudo apt-get install python3.7

Install graphviz

 % sudo apt-get install -y graphviz

Install Verilator

Verilator is an open-source toolchain for compiling Verilog RTL models into C++ simulators. OpenCGRA uses Verilator for Verilog import.

 $ sudo apt-get install git make autoconf g++ libfl-dev bison
 $ mkdir -p ${HOME}/src
 $ cd ${HOME}/src
 $ wget http://www.veripool.org/ftp/verilator-4.036.tgz
 $ tar -xzvf verilator-4.036.tgz
 $ cd verilator-4.036
 $ ./configure
 $ make
 $ sudo make install

Install git, Python headers, and libffi

We need to install the Python headers and libffi in order to be able to install the cffi Python package. cffi provides an elegant way to call C functions from Python, and PyMTL uses cffi to call C code generated by Verilator. We will use git to grab the PyMTL source. The following commands will install the appropriate packages:

 % sudo apt-get install git python-dev libffi-dev

Create virtual environment

While not strictly necessary, we strongly recommend using virtualenv to install PyMTL3 and the Python packages that PyMTL3 depends on. virtualenv enables creating isolated Python environments. The following commands will create and activate the virtual environment:

 % python3 -m venv ${HOME}/venv
 % source ${HOME}/venv/bin/activate

Install PyMTL3 and Python requirements

 % pip install git+https://github.com/tancheng/pymtl3.git
 % pip install --upgrade pip setuptools twine
 % pip install hypothesis
 % pip list

Clone OpenCGRA repo

We can now use git to clone the OpenCGRA repo.

 % mkdir -p ${HOME}/cgra
 % cd ${HOME}/cgra
 % git clone https://github.com/pnnl/OpenCGRA.git

Run an example to generate Verilog

In folder, just type:

 % pytest --tb=short -sv CGRARTL_test.py

When you're done testing/developing, you can deactivate the virtualenv::

 % deactivate

opencgra's Issues

Question about RTLtest

Hello,
I noticed in the paper it is mentioned OpenCGRA will read control signal for simulation at RTL, but I didn't find the relevent code in CGRARTL_test.py in the test folder and was a little bit confused about how to load the control signal to start RTL simulation. It would be nice if you could provide some hint about this.

Thanks in advance!

Questions about running CGRACL_FIR_demo_test.py

Hi, sorry to bother you. I have configured the running environment and run pytest on script CGRACL_FIR_demo_test.py and then I get the following live out result.
CL simulation outcome

FL simulation outcome

source kernel

My question is how can I correspond the final live out result of FL simulation and CL simulation with the variable value of the cpp source kernel code and I do not understand the meaning of outcome tile bits value. Appreciate it a lot if you can help!

How to run the design for a specfic application

Hi, thanks for opening the valuable work.

I have a hard time figuring out how to run the OpenCGRA. might I ask how to run the CGRA to launch CL, FL and RTL level simulation and generate RTL for any application?

Thanks in advance.
JT

How to to generate control signals with the compiler?

Hi,
I generated Verilog code from RTL code with the generator. Now I want to configure it for my application. But I am confused about generating the .json file with the compiler and configure it to the control memory. Is there any tutorial or example I can refer to?

Thank you!

Differences in CGRAFL expected DFG and CGRA Mapper generated DFG,json

Hi,

I'm using the https://github.com/tancheng/CGRA-Mapper to map some new kernels to this, but the dfg.json generated has the following field names changed:

opt -> JSON_opt
in -> pre
out -> succ

and the predicate fields removed altogether. The DFG class requires these fields and so the CGRAFL fails as a result. Should I be using a particular version of the cgra-mapper?

install BUG

Hi,Cheng：
I'm very glad to meet such a strong CGRA simulator!
After I followed the instruction step by step, I met the error:
=================================== FAILURES ===================================
_____________________________ test_cgra_universal ______________________________
CGRARTL_test.py:116: in test_cgra_universal
DataType = mk_data( 32, 1 )
../../lib/messages.py:36: in mk_data
namespace = { 'str': str_func }
/home/ai/venv/lib/python3.7/site-packages/pymtl3/datatypes/bitstructs.py:557: in mk_bitstruct
add_repr=add_repr, add_hash=add_hash )
/home/ai/venv/lib/python3.7/site-packages/pymtl3/datatypes/bitstructs.py:529: in bitstruct
return wrap( _cls )
/home/ai/venv/lib/python3.7/site-packages/pymtl3/datatypes/bitstructs.py:522: in wrap
return _process_class( cls, add_init, add_str, add_repr )
/home/ai/venv/lib/python3.7/site-packages/pymtl3/datatypes/bitstructs.py:457: in _process_class
cls.init = _mk_init_fn( _get_self_name(fields), fields )
/home/ai/venv/lib/python3.7/site-packages/pymtl3/datatypes/bitstructs.py:191: in _mk_init_fn
_globals = _globals,
/home/ai/venv/lib/python3.7/site-packages/pymtl3/datatypes/bitstructs.py:107: in _create_fn
custom_exec( py.code.Source(src).compile(), _globals, _locals )
E AttributeError: module 'py' has no attribute 'code'

by the way:
============================= test session starts ==============================
platform linux -- Python 3.7.1, pytest-7.4.4, pluggy-1.2.0 -- /home/ai/venv/bin/python3
cachedir: .pytest_cache
hypothesis profile 'default' -> database=DirectoryBasedExampleDatabase('/home/ai/cgra/OpenCGRA/cgra/translate/.hypothesis/examples')
rootdir: /home/ai/cgra/OpenCGRA
configfile: pytest.ini
plugins: pymtl3-0.5.5.1, hypothesis-6.79.4
collected 1 item

Could you help me? Have a nice Day!
Thanks!

Limited support for phi node

Currently, we can only support PHI nodes that are accompanied by CMP nodes (i.e., a problem caused by the implementation of phi node in the functional unit architecture). We might provide a new design of the PHI node in both the DFG and RTL in the future.
For now, it is better to manually change the following code:

  for(int x=0; x<total; ++x) {
    int i = x / maxNodeCount;
    int j = x % maxNodeCount;
    if(matrix[i][j] != 0) {
      value[index] = matrix[i][j];
      row[index] = i;
      col[index] = j;
      index++;
    }
  }

to:

  for(int x=0; x<total; ++x) {
    int i = x / maxNodeCount;
    int j = x % maxNodeCount;
    value[index] = matrix[i][j];
    row[index] = i;
    col[index] = j;
    if(matrix[i][j] != 0) {
      index++;
    }
  }

AURORA's code has not been open-sourced?

Hi Tancheng,

I'd like to have a look on the code of AURORA, but I did not find it in OpenCGRA or other repositories, so I think it has not been open-sourced yet, right?

And will it be an open source project in github in the future? Thank you Tancheng!

Best Regards.

Question about how to obtain evaluation indicators for tasks

Hi,Cheng,
Recently, I was working on the topic of Microarchitecture space exploration based on the OpenCGRA framework, but I encountered some problems. For a. cpp file, we use CGRA Mapper to map it to a specific architecture and generate related files. , but how can we obtain the execution time of the tasks described in the. cpp file in a specific architecture.
Have a nice Day!
Thanks!

CGRA Power Consumption Report

Hi,

How I can use your tool to obtain power consumption for FIR filter application?

Thank you.

Error trying to convert [s.dut.tile[0].element.fu[0], s.dut.tile[0].element.fu[1]] into RTLIR:

Getting errors when running CGRARTL_test.py with py.test under the cgra/translate directory:

E pymtl3.passes.rtlir.errors.RTLIRConversionError:
E In file /home/e24066331/venv/lib/python3.6/site-packages/pymtl3/passes/rtlir/rtype/RTLIRType.py, Line 481, Method _handle_Array:
E Error trying to convert [s.dut.tile[0].element.fu[0], s.dut.tile[0].element.fu[1]] into RTLIR:
E - all elements of array [s.dut.tile[0].element.fu[0], s.dut.tile[0].element.fu[1]] must have the same type Component!
E f'all elements of array {obj} must have the same type {ref_type}!'

It might have to do with the FuList but still not sure where the problem is.
I cloned the whole repo down on my computer without any modifying.

Question about run test

Hi,
sorry to bother you, but I encounter a problem running the demo.
I am new to OpenCGRA and I am trying to run the CGRACL_FIR_demo_test.py. However, I am not sure where should I start.
If I use

python3 ./cgra/test/CGRARTL_test.py

Then I will get

Traceback (most recent call last):
  File "./cgra/test/CGRARTL_test.py", line 16, in <module>
    from ...lib.opt_type              import *
ImportError: attempted relative import with no known parent package

If I use

./cgra/test/CGRARTL_test.py

I would get

./cgra/test/CGRARTL_test.py: line 10: $'\n==========================================================================\nCGRARTL_test.py\n==========================================================================\nTest cases for CGRAs with different configurations.\n\nAuthor : Cheng Tan\n  Date : Dec 15, 2019\n\n': command not found
from: can't read /var/mail/pymtl3
from: can't read /var/mail/pymtl3.stdlib.test
from: can't read /var/mail/pymtl3.stdlib.test.test_srcs
from: can't read /var/mail/...lib.opt_type
from: can't read /var/mail/...lib.messages
from: can't read /var/mail/...fu.flexible.FlexibleFuRTL
from: can't read /var/mail/...fu.single.AdderRTL
from: can't read /var/mail/...fu.single.ShifterRTL
from: can't read /var/mail/...fu.single.MemUnitRTL
from: can't read /var/mail/..CGRARTL
./cgra/test/CGRARTL_test.py: line 29: syntax error near unexpected token `('
./cgra/test/CGRARTL_test.py: line 29: `class TestHarness( Component ):'

But when I use py.test, it can pass the test.
Is there any tutorial or example I can refer to?
Thank you!