Topic: picorv32 Goto Github
Some thing interesting about picorv32
Some thing interesting about picorv32
picorv32,Physical Design Flow from RTL to GDS using Opensource tools.
User: akilm
Home Page: https://www.vlsisystemdesign.com/
picorv32,This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the accelerator with gradual improvements through spatial pre-computation techniques and pipelining. The SHA256 accelerators are implemented using Verilog and synthesized using Yosys Open Synthesis Suite. The optimized designs are then compared with a base-line C implementation in software. Hash functions are used to securely store passwords, to quickly store and retrive data, and also to check if a file/message is corrupted.
User: antonson-j1
picorv32,C examples for picorv32 CPU
User: jesus89
picorv32,Minimal system project with riscv core picorv32 : asm startup + linker script + c example + verilog system + testbench + Makefile
User: jokleinge1
picorv32,Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations
Organization: lnis-uofu
Home Page: https://openfpga-softcores.rtfd.io
picorv32,Xilinx FPGA loader
User: majorlin
picorv32,c compiler beluga with riscv32 backend
User: michg
picorv32,5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD
Organization: riscv-myth-workshop
picorv32,A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
User: wuhanstudio
picorv32,A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)
User: wuhanstudio
picorv32,A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
User: wuhanstudio
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