Daugther board schematics?

[ks10fpga]

Daugther board schematics?

[jfcl]

There are schematics. I still don't have working SSRAM so I haven't posted them publicly. I don't expect there to be problems - but, they come with no warranties. I've attached them here.

DE10-Nano-IO_SH2_RD04.pdf
DE10-Nano-IO_SH1_RD04.pdf

[jfcl]

It is actually a fairly nice device to mate with a 36-bit processor. You can find a Verilog model for the memory device.

What you can't tell from the schematic is RAM-ADV is negated by the FPGA always (I could have wired it to ground). The FPGA does a 2 word burst: A0 is always negated on the first word and always asserted on the second word. All the other address lines are just shifted up one bit.

In my implementation a memory operation requires four clock cycles. I clock the memory four times faster than the CPU so the CPU thinks that the memory is running at CPU speed.

The chip is smart. It pipelines the data bus direction (and the data) with the WE# pin.

I've attached a rough timing diagram in case you're interested.

[ams]

Thank you! Was actually interested in the SSRAM part, wondering if it could be used for inspiration in my MIT CADR work.

[ams]

Thank you for the description, it does looks like a very nice little chip.

I need to think a bit further, since the CADR requires an actual console, keyboard and mouse. Which takes up several wires from the FPGA. The Arty exposes some using a PMOD external interface, and some using some sort of Arduino header. Plus, I am not entirely sure I need the extra RAM, but SRAM is so much easier to interface than DDR and using MIG.

[jfcl]

I've finally debugged and verified that the KS10 memory is working properly. There are a few changes and the status will be maintained at:

https://github.com/KS10FPGA/KS10FPGA/wiki/Memory-Controller-and-Memory#ssram-memory-interface