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jfcl avatar jfcl commented on June 19, 2024

The current implementation does the following:

SMMON CMD - DSKEB
DSKEB - KS10 CACHE DIAGNOSTIC
VERSION 0.1, SV=0.3, CPU#=2020, MCV=130, MCO=470, HO=0, KASW=000000 000000

TTY SWITCH CONTROL ? - 0,S OR Y  - 0
SWITCHES = 000000 000000

PC=  032044
SWITCHES = 000000 000000
ERROR IN DSKEB - KS10 CACHE DIAGNOSTIC VERSION 0,1 - PHYSICAL EXEC CACHE CHECK
ACTUAL:   000000 001520
CACHE HITS WHEN MISSES EXPECTED

This is the expected results. The diagnostic measures the execution time of a simple loop with the cache enabled and with the cache disabled. The diagnostic expects the execution time of the un-cached loop to be longer than the cached loop.

As noted above, the KS10 FPGA uses single-cycle synchronous SRAM for main memory which operates as fast as a cache would - therefore the execution time is identical.

I could add a conditional compile which adds a wait-state to main memory when the cache was disable in order to provoke this diagnostic to pass.

from ks10fpga.

jfcl avatar jfcl commented on June 19, 2024

Won't fix.

from ks10fpga.

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