laforest/fpgadesignelements

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

FPGA Design Elements

Copyright (c) 2019-2020 Charles Eric LaForest, PhD.

A self-contained online book containing a library of FPGA design elements and related coding/design guides.

You can read it online at http://fpgacpu.ca/fpga/

To obtain your own local copy:

git clone https://github.com/laforest/FPGADesignElements.git

then access index.html from your favourite browser.

All files are in one directory, so you can use it as a library in your CAD tools by simply importing all Verilog files.

IMPORTANT: The module definitions are, by design, not usable as-is. Unless the design requires some minimum or constant value, all module parameters have a default value of 0 or an empty string. This is intentional, so when a user forgets to set a parameter when instantiating a module, synthesis will (almost always) fail, and linting also. Putting usable default values in the module definitions might not get noticed and cause bugs. This means the modules are not synthesizable as defined, but must be instantiated separately to set the parameters, which is what one normally does anyway.

See LICENSE for the details, but overall, you are free to use this book as you please.

Contributions are welcome. Please email [email protected] or Twitter @elaforest or join the Discord server.

fpgadesignelements's Issues

Missing Width_Extender module

Hi @laforest. The module Width_Extender is referenced in some other modules such as Adder_Subtractor_Binary_Saturating.v and Adder_Subtractor_Binary.v, but is not in the repository.

CAM implementation

Hi there, I'm looking for a CAM implementation, the "FPGA Design Elements" is lack of CAM related content.
Would you please kindly share with me some resource/documents on CAM?
Thanks!

Constant.v:24: warning: @* found no sensitivities so it will never trigger.

It is a complaint from iVerilog. The problem is here (because nothing is changed inside of the always):

    always @(*) begin
        constant_out = VALUE;
    end

What about to use an assign instead? Something like:

module Constant
#(
    parameter WORD_WIDTH    = 0,
    parameter VALUE         = 0
)
(
    output wire [WORD_WIDTH-1:0] constant_out
);

    assign constant_out = VALUE;

endmodule

Let me know if you agree with the suggested change to create a PR.

PS: is only a warning, which could have not a negative effect, but in this form is simpler and the warning removed.

Function body with multiple statements requires SystemVerilog

The last complaints of iVerilog (over two files):

Binary_to_Gray_Reflected.v:1: error: Function body with multiple statements requires SystemVerilog.
Gray_to_Binary_Reflected.v:1: error: Function body with multiple statements requires SystemVerilog.

Possible syntax error at Pipeline_FIFO_Buffer.v

Hi @laforest. I was updating my Verifying FOSS HDL-synthesizers project, and there is an error with Pipeline_FIFO_Buffer.v. There are no iverilog or verilator complaints, but Yosys says:

-- Running command `read_verilog -defer examples/Pipeline_FIFO_Buffer.v;' --

1. Executing Verilog-2005 frontend: examples/Pipeline_FIFO_Buffer.v
examples/Pipeline_FIFO_Buffer.v:107: ERROR: syntax error, unexpected ')'

The problem is here (at line 107):

    RAM_Simple_Dual_Port
    #(
        .WORD_WIDTH         (WORD_WIDTH),
        .ADDR_WIDTH         (ADDR_WIDTH),
        .DEPTH              (DEPTH),
        .RAMSTYLE           (RAMSTYLE),
        .READ_NEW_DATA      (0),
        .RW_ADDR_COLLISION  ("no"),
        .USE_INIT_FILE      (0),
        .INIT_FILE          (), // <---- Problem here
        .INIT_VALUE         (WORD_ZERO)
    )
    buffer
    (

I never saw the specification of an empty parameter (yes in signals/ports, where it means no connection). Could you verify if it is legal?

Regards,
Rodrigo

Problems with zero or negative widths

Hello @laforest . I have a repo where the idea is to test Yosys against a lot of synthesizable hardware descriptions. I added a directory called FPGADesignElements (in a branch).

The thing is, that I checked your examples with iverilog and the verilator linter, and there are mainly errors related to 0 or negative widths. One example:

* examples/Bitmask_Next_with_Constant_Popcount_ntz.v
examples/Word_Reducer.v:32: error: Concatenation repeat may not be zero in this context.
examples/Logarithm_of_Powers_of_Two.v:103: error: Concatenation repeat may not be zero in this context.
examples/Logarithm_of_Powers_of_Two.v:78: error: Concatenation repeat may not be zero in this context.
examples/Logarithm_of_Powers_of_Two.v:61: error: Concatenation repeat may not be zero in this context.
examples/Adder_Subtractor_Binary.v:31: error: Concatenation repeat may not be zero in this context.
examples/Bit_Shifter.v:82: error: Concatenation repeat may not be zero in this context.
examples/Bit_Shifter.v:83: error: Concatenation repeat may not be zero in this context.
examples/Bitmask_Next_with_Constant_Popcount_ntz.v:64: error: Concatenation repeat may not be zero in this context.
8 error(s) during elaboration.

Without further analysis of each situation, I understand that the problems are related to parameters with the value 0, which seems invalid (so, I think that are not good default values).

In the branch of my repo, there is a Makefile to download the examples and run iverilog and verilator. You can test there. Also, if you want, I can contribute with a Makefile (or bash, let me know what you prefer) for your repository.

Consider deploying to github pages

It would increase the accessibility of your book and it's not very hard to set up.

Consider adding Verible and/or Surelog to verilinter?

You might want to consider adding Google's Verible and/or Surelog to your verilinter script. Verible provides precompiled binaries for most common Linux systems and is under <10mb it seems.

Verible can also be used to do code formatting if that is of interest.

Both Surelog and Verible should be able to parse anything that Icarus and Verilator can already parse, if you start using them and find anything which doesn't, please do log bugs on the associated repositories.

Verilator complain about Carryin_binary.v

Let me start saying that, after patch the 0 values/empty-strings of your files, it is the only remain Verilator complain :-) (there are still some iverilog complains, may be also related with other things to be changed).

%Warning-WIDTH: examples/CarryIn_Binary.v:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits.

It can be solved changing carryin = 1'b0; by carryin = {WORD_WIDTH{1'b0}}; in the initial block. I don't know if you accept PR (let me know for future cases).