lulinchen/cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

A CNN(Convolutional Neural Network) hardware implementation

This project is an attempt to implemnt a harware CNN structure.

The code is written by Verilog/SystemVerilog and Synthesized on Xilinx FPGA using Vivado.

The code is just experimental for function, not full optimized.

Architecture

Only 4 elementary modules implemented:

• The conv, this module perform the convolution computing, the full connecting is also treated the same as convolution with the kernel size equal to input data size.
• The max_pool
• The relu
• The iterator, jogging around the input data, and feed the computing units.

Demo

A LeNet is constructed using the 4 elementary modules, the weights and biases are hard coded in ROM.

The reference Tenserflow Lenet code is from CarND-LeNet-Lab .

Xilinx KCU105 Board, with HDMI input and output daughter boards is used.

Connect a PC to the HDMI input daughter through a HDMI cable.

A 32x32-size input is cropped from the PC screen output, then fed into the Lenet. The classified result is displayed on the HDMI output.

The following pic is cropped from the HDMI output of FPGA. The white rectangle is draw by FPGA. Move a Mnist digit picture into the rectangle, or draw a digit by hand using a Paint software. The printed digit under the rectangle is the the classified result.

Conclusion

• Pure RTL hardware design is not a good choice for neural networks. Especially for large scale networks, the weights and intermediate results need to be stored in external memory. And the data iterator will be more complex. It's better to use a general or specific processor to do the control works, and let the hardware to perform computing.

Reference

CarND-LeNet-Lab .

Author

LulinChen
[email protected]

cnn_open's Issues

Where is your "global.v"?

Hi, I can't find your "global.v". I will appreciate it a lot if you can reply.

How to start the porject?

Hi, I very happy I found a person project same as like me. Your project is very help for me as a reference..
BTW, how can i open your project for your source files by using vivado? I mean where is the directory. Thank for you help

prediction accuracy

Hi, may I ask that how much accuracy your project can achieve ? Any reply will be appreciated.

How to start your project and verify this result?

Hello, I am a beginner in Vivado and FPGA.
So I encountered some difficulties, I got an error when run lenet_ku.tcl, like
"Design fails in opt_design with a black-box error"

Whether after run tcl is

1. File -> Import -> Export Hardware
2. File -> Launch -> Launch SDK

And the question is what is your version of vivado ?

Thank you !!

syntax errors

Hello! There are many syntax errors in the cnn.v module, as shown in Figures 1, 2, and 3
fig1:

fig2:

fig3:

fig4: