openhwgroup/cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cva6's Issues

Address translation in MMU

I want to perform address translation using the MMU. Currently my core is running in M mode wherein i don't have the capability to perform the address translation.

What all changes has to be done to get the address translation to work. Like where in the ISA should i change? Are there any changes to the core that i have to do with respect to this?

License problem in axi_mem_if_wrap.sv

axi_mem_if_wrap.sv still has a license inconsistent with the whole repository. This file should be removed or reconciled with the license of the whole.

can i Synthesis the core using Vivado

can i use the source code to simulate and Synthesis using vivado
whenever i use the source system verilog file and trying to run i get multiple errors

HPTW

Why does both the TLBs get updated from the data read from the DCache?

https://github.com/pulp-platform/ariane/blob/a006526c6f1b9cab24dc6b39a672036c7f014f46/src/ptw.sv#L119-L131

Here the pte is nothing but the data read from the DCache. Then when the PTW goes for a walk to perform the PTE lookup then aren't we looking at the wrong entry for the ITLB ?
Can you explain it please?

Renaming uses rs1 index for both rs1 and rs2

https://github.com/pulp-platform/ariane/blob/b3a337eccc0e8f7af09e9fc4e5be40aaeebafdd9/src/re_name.sv#L59

shouldn't it be fixed to re_name_table_q[issue_instr_i.rs2] ?

error ./includes

I used the following command but I have a error with the includes : make build;

....
In the directories I found the include file, but vlog not.

Can someone help me ?

Make verilator

Hi, I am getting the following issue while running "make verilate" command:

[Question] Code & Functional Coverage?

Hi All

This is a question rather than an 'issue' - apologies if I am asking it in the wrong place, I'm happy to close this and ask it again there.

How do you collect code coverage and functional coverage numbers from your verification environment? I'm working on a similar project and am stuck in terms of what tools support. What you used to verify against (as a reference model) and check you were covering different conditions the tests say they should?

Thanks,
Ben

Questasim uvm_dpi.so

HI,

I have build the TB and module with questasim 10.6c_3. I start the simulation : make simc (without GUI)

I have the following warning :

Now I run (run -a) :

How can I solve this error ? where does it come from ?
I have only add -64 in the scipt.

Thanks in advance.

PTW protocol violation if during pipeline flush

The PTW has an illegal state in which it can violate the req, gnt protocol (from PTE_LOOKUP to IDLE during flush).

https://github.com/pulp-platform/ariane/blob/838b04a96c45cee81ce658492baf74f117357dd2/src/ptw.sv#L331-L338

Example execution trace:

1127755000     112766 U 0000000000005fce 0 00000013 nop                                 
1127765000     112767 U 0000000000005fd0 0 00ee579b srliw            a5, t3, 0xe         x15 =0000000000000000 t3  :0000000000000000
1127775000     112768 U 0000000000005fd4 0 0000100f fence.i                             
1132915000     113282 U 0000000000005fd8 0 40755b3b sraw             s6, a0, t2          x22 =ffffffffffffffff a0  :ffffffffffffffff t2  :0000000000000000
1132925000     113283 U 0000000000005fdc 0 12000073 sfence.vma                          
1133245000     113315 U 0000000000005fe0 0 00000000 INVALID                             
Exception @1133245000, PC: 0000000000005fe0, Cause: Instruction Page Fault, 
tval: 0000000000005fe0

Should debug_set_pc_i set flush_icache (how else do we inform a new program is loaded ?)

Extract from controller.sv line approx 137
// ---------------------------------
// 1. Exception
// 2. Return from exception
// 3. Debug
// ---------------------------------
if (ex_valid_i || eret_i || debug_set_pc_i) begin
// don't flush pcgen as we want to take the exception: Flush PCGen is not a flush signal
// for the PC Gen stage but instead tells it to take the PC we gave it
flush_pcgen_o = 1'b0;
flush_if_o = 1'b1;
flush_unissued_instr_o = 1'b1;
flush_id_o = 1'b1;
flush_ex_o = 1'b1;
// flush branch-prediction - it is difficult to say whether this actually loses performance or increases performance
// because of reduced mis-predicts. There is one case where flushing branch-prediction is absolutely necessary
// that is when trapping back to machine mode. As the core is making speculative accesses it can happen that it tries
// to load from an non-idempotent register where a read can have a side-effect. This can happen as the core can try to load
// from a user-mode address which is then not translated in machine-mode.
flush_bp_o = 1'b1;
// Should we flush icache here when the debugger sets the PC ?
if (debug_set_pc_i)
flush_icache_d = 1'b1;
end
end

Potential L1 dcache issues

I have a memory test program that goes wrong as soon as the range is increased to 64K bytes (this is in a large behavioural memory). I have racked my brains and cannot think of a reason unless it is to do with L1-cache misbehaviour.

cd tmp/riscv-tests
git remote remove origin
git remote add origin https://github.com/jrrk/riscv-tests.git
git fetch
git checkout -b ariane_memtester
cd build
make
cd ../../..

xxx@xxx:/local/scratch/jrrk2/ariane-isatest$ obj_dir/Variane_wrapped tmp/riscv-tests/build/benchmarks/memtester.riscv

Bare metal DRAM test
memtester version 4.3.0 (64-bit)
Copyright (C) 2001-2012 Charles Cazabon.
Licensed under the GNU General Public License version 2 (only).

test range is 0x800134f0 to 0x800234ef
Loop 1/1:
ok         3 3 2 2 1 1 0 0
  Random Value: FAILURE: 0x7ffecaaf != 0xfff99a4c at offset 0x60.
p1 = 0x80013550, p2 = 0x8001b550
xxx@xxx:/local/scratch/jrrk2/ariane-isatest$ git status
On branch master
nothing to commit, working directory clean
xxx@xxx:/local/scratch/jrrk2/ariane-isatest$

(This output takes about 10 minutes to appear on my workstation)

I hope you can reproduce the above. If you succeed it in fixing it some strange things will happen perhaps when byte writing is tested because your ram model does not support this mode.

Error in "make build"

Hi,

I am getting following error in "make build"

g++ -c -fPIC -m64 -std=c++0x -I/include -shared -o work/elf_dpi.o -c tb/dpi/elfdpi.cc
tb/dpi/elfdpi.cc:26:22: fatal error: vpi_user.h: No such file or directory

Can you please help me with that?

Farhad

Generate hex file

What is the command to generate .hex from .elf for Questasim?

I used the following command but not sure that is correct (just run few ISA tests and they worked fine but when I run rsort benchmark, it is run out memory)

elf2hex 8 16384 hello.riscv 2147483648 > hello.riscv.hex 

[Feature] Handle Bus Errors correctly

At the moment bus errors are not resolved. Mostly because the AXI infrastructure does not support bus errors.

module btb not used at all modules

Hi, I am reading your code and I found out that you wrote a btb module but it is never used any where in this design. I feel like you intended to use it in pcgen_stage.sv and you already set up input and output signals for btb but somehow you decided remove btb from pcgen.

Is this intentional for future developmen?

Yongqin

BTB not active

The branch target buffer seems dead. Need to debug this performance problem asap.

Error in elf2hex

Hi,

I am getting following error in generating hex file

elf2hex 8 2097152 /net/home/merchantf/Downloads/riscv-tools/hello 2147483648  > hello.hex
elf2hex: ../fesvr/htif_hexwriter.cc:17: virtual void htif_hexwriter_t::read_chunk(addr_t, size_t, void*): Assertion `taddr < width*depth' failed.

Can you help me with this?

Extraneous decoder condition

This might seem somewhat perfectionist, but there seems to be an extraneous line in the decoding logic. I am talking about the line 273 in the following excerpt.

https://github.com/pulp-platform/ariane/blob/3c6e29f23b3559fffe6532326a77a7d741ee3d53/src/decoder.sv#L267-L274

Invalid OPCODE_OP32 instructions that have their 28th-bit set would not reach the unique_case and would not be marked as invalid (as in this process the default assignment is illegal_instr = 1'b0).

VCS compile error with miss_handler.sv

VCS is complaining about this line:
https://github.com/pulp-platform/ariane/blob/master/src/miss_handler.sv#L687
logic [$clog2(DATA_WIDTH/64)-1:0] cnt_d, cnt_q;

When DATA_WIDTH = 64, this expression becomes "logic[-1:0] cnt_d, cnt_q;", which looks incorrect

Here's the related instance with DATA_WIDTH = 64
https://github.com/pulp-platform/ariane/blob/master/src/miss_handler.sv#L424

Forwarding of FP registers

There is a potential problem with the forwarding logic of floating point registers.

https://github.com/pulp-platform/ariane/blob/8620f41ea1db93c7883844011092147a23cabab3/src/scoreboard.sv#L217-L220

In the excerpt above, it is the destination register of mem_q[i] that is being forwarded as source register of issue_instr_o. Because of this, I think the correct check should be is_rd_fpr(mem_q[i].sbe.op) == is_rs1_fpr(issue_instr_o.op) instead. There are more cases of this throughout the scoreboard.

---

Also, in is_rd_fpr (and is_rs2_fpr), shouldn't the test below go up to [FLD:FLB] instead of stopping at FLW?

https://github.com/pulp-platform/ariane/blob/8620f41ea1db93c7883844011092147a23cabab3/include/ariane_pkg.sv#L253-L256

Is elfdpi.h missing from the repo ?

elfdpi.h is referenced in elfdpi.cc but doesn't seem to be present or generated anywhere.

Dead-code elimination

PCIMM and BIMM are never needed.

https://github.com/pulp-platform/ariane/blob/35105da7346d3e8c9f6872458330aee76e9281aa/src/decoder.sv#L515-L548

ISA Tests

I ran ISA test with elf file rv64ud-v-fadd.

Output I see when I run following command
make simc riscv-test=rv64ud-v-fadd

### _**# do tb/wave/wave_core.do
VSIM 2> run
# ----------------------------------------------------------------
# UVM-1.1d
# (C) 2007-2013 Mentor Graphics Corporation
# (C) 2007-2013 Cadence Design Systems, Inc.
# (C) 2006-2013 Synopsys, Inc.
# (C) 2011-2013 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM]  questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [Program Loader] Pre-loading memory from file: /net/home/merchantf/Downloads/riscv-tools/riscv-tests/build/isa/rv64ud-v-fadd
# 
# UVM_INFO @ 0: reporter [Program Loader] tohost: 0000000080001000 begin_signature 0000000080003140
# 
# UVM_INFO @ 0: reporter [RNTST] Running test core_test...**_

Is this expected output?

I am not sure why, but formatting of text does not seem to work here on copy pasted text.

[Feature] A-Extension Support

This issue targets the long needed atomic memory support.

Tasks

• Add support to execute AMOs without any of the ordering bits set
• Add support for aq and rl bits
• Work on adding LR and SC instructions

Overview

General there are 4 cases:

acquire semantic: If the aq bit is set, then no later memory operations in this RISC-V hart can be observed to take place before the AMO.
-> block issue until the atomic memory operation is resolved, wait on commit signal, flush cache, do AMO, write back

release semantic: If the rl bit is set, then other RISC-V harts will not observe the AMO before memory accesses preceding the AMO in this RISC-V hart.
-> block issue until no more outstanding loads (trivially met as the load unit will implicitly synchronize, structural hazard) or stores (wait for store buffer to drain), wait on AMO commit, flush cache, do AMO, write-back

sequentially consistent: If both the aq and rl bits are set, the atomic memory operation is sequentially consistent and cannot be observed to happen before any earlier memory operations or after any later memory operations in the same RISC-V hart, and can only be observed by any other hart in the same global order of all sequentially consistent atomic memory operations to the same address domain.
-> block issue until no more outstanding loads or stores, issue atomic, wait on commit signal, block issue until atomic comited, flush dcache, do amo, write-back

unordered: aq and rl not set -> just issue -> wait for amo_commit -> flush dcache -> do AMO -> write back AMO

Details

• Decoder (decoder.sv): The atomic instruction needs to be properly decoded. Most of the operations are there but this needs some further checking (especially if all parameters are set properly and illegal instructions are thrown in case of an illegal instruction with the OPCODE_AMO).
  Decoder will also need to block the decoding of any subsequent instructions in case the instruction requires release, acquire or sequential consistency. There is already an amo_commit_i signal which indicates that the atomic memory operation finished. If we block the issue stage we need to un-block it if the controller wants to flush.

• LSU - Data Cache (lsu.sv, nbdcache.sv, cache_ctrl.sv): Those units will require the biggest amount of changes. Basically every atomic instruction should be treated as a load (because even the stores will return something: success or not). So we need to route those instructions similar to a load. The load unit will interface the dcache with an additional signal amo_t amo_op_o indicating whether the current operation is atomic (and which operation) or a regular load.
  In case it is an atomic operation the cache_ctrl FSM will enter a new state saving all information (address, op to perform, etc.) and wait for the amo_commit_i signal to go high or for amo_flush_i to go high. If the latter happens it will return to the idle state. If the amo_commit_i signal goes high the cache controller should flush the data cache and issue a new transaction on the bypass signal once the flush is done.
  Here we need to differentiate between LR/SC and the AMO OPs. LR/SC will need to use the AXI Lock infrastructure (see AXI Interface specification) to place a reservation (we will need to adapt the testbench for that) while the AMO OPs can retrieve the data process it locally with the AMO ALU. In every case the atomic memory operations will return some result on the amo_result_o signal together with a high amo_valid_o. Both signals go to the commit stage.

One further thing which needs a fix is to increase the the width of the dirty SRAM so that it holds a dirty bit per byte. The flush/cache line write-back logic needs to set the corresponding wstrb bits. That is because Ariane does not support cache-coherency at the moment and we need to explicitly take care of write-sequentialisation.

• Commit Stage (commit_stage.sv): This unit will need to look at the retiring instruction and see that it is an atomic instruction. If it is an atomic instruction the commit stage will assert the amo_comit signal for one cycle and block committing new instructions until the amo_valid_o is high and indicating a successful atomic memory operation. It will commit the result into the register file. And continue comiting new instructions.

Feel free to check-back, clarify, hack-away.

Move branch comparisons to ALU

There are some potential area savings when moving the branch comparisons to the ALU. This will also ease timing on the write back path to the scoreboard/ROB.

icache corruption

When Ariane's instruction and data interfaces are connected to the same memory via a crossbar, you do not want data with a different ID to be returned to the wrong port. However in icache.sv, not only is the master ID 0, but the returned ID is not checked so any old rubbish can get into the icache as below:

--- a/src/icache.sv
+++ b/src/icache.sv
@@ -208,7 +208,8 @@ module icache #(
end
endgenerate

• assign refill_ID_to_comp = '0;
  +// This master ID is a placeholder. Unique IDs need to come from a central pool ...

• assign refill_ID_to_comp = '5;

  lint_to_axi_refill #(
  .FETCH_ADDR_WIDTH ( FETCH_ADDR_WIDTH ), //= 56,
  @@ -310,7 +311,8 @@ module lint_to_axi_refill #(
  assign axi.r_ready = 1'b1;

  assign refill_gnt_o = axi.ar_ready;

• assign refill_r_valid_o = axi.r_valid;
  +// Don't accept valid signals that don't match our master ID...

• assign refill_r_valid_o = axi.r_valid && (axi.r_id == refill_ID_i);
  assign refill_r_ID_o = axi.r_id;
  assign refill_r_data_o = axi.r_data;
  assign refill_r_last_o = axi.r_last;
  @@ -747,7 +749,7 @@ module icache_controller #(
  if (save_fetch_way)
  fetch_way_Q <= fetch_way_int;

•        //Use this code to be sure thhat there is not apending transaction when enable cache request is asserted
  

•        //Use this code to be sure that there is no pending transaction when enable cache request is asserted
         if (CS == DISABLED_ICACHE || CS == WAIT_PENDING_TRANS) begin
             case ({(refill_req_o & refill_gnt_i), refill_r_valid_i})
                 2'b00: begin pending_trans_dis_cache <= pending_trans_dis_cache;       end
  

Instruction start at 0x80000000

Why is there a specific need for the instruction to start at 0x80000000?

MSTATUS.MIE is written unexpectedly when programming SSTATUS

MSTATUS.MIE is enabled first, however, the value is overwritten when SSTATUS is programmed. SSTATUS[3] is a WPRI field, hardware should ignore this write and preserve the current value.

License inconsitency in axi_mem_if_wrap.sv

vsim-5 error

When I am doing run -all command in vsim, I am getting this error.

Can anyone help me with this?

Add RISC-V compliant debug

• Remove legacy debug
• Implement changes to core
• Implement debug module
• Implement debug transport module
• Run RISC-V tests
• Verify single-step behavior
• remove elf2hex section from the readme
• Check that abstractcs progbuf size is checked correctly.
• Verify riscv-pk functionality
• Handle reset more gracefully

typo in src/ariane_wrapped.sv

The bypass interface in ariane_wrapped.sv refers to data_address when bypass_address is intended
// ------------------------
// Bypass Interface
// ------------------------
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
bypass_rdata <= '0;
end else begin
if (bypass_req & bypass_we)
write_uint64({data_address[63:3], 3'b0}, bypass_wdata);
else if (bypass_req)
bypass_rdata <= read_uint64({bypass_address[63:3], 3'b0});
end

Instruction trace when using Verilator

Hi,

When using Verilator for running ELFs, I see that only the performance numbers are printed on stdout. Apart from that we can dump the signals to create a .vcd file. Wanted to know if there is an option to dump the executed instruction trace as well (similar to the way we see on Questasim)? That would make debugging easier when working with Verilator.

Thank you!

run dhrystone with questasim

Hi, I am getting the following issue while running dhrystone in questasim 10.6 :

I have generate an elf and an hex.

Can someone help me ?

Error Elaborating Ariane using Genus

Hello,

I'm trying to synthesize Ariane using Cadence Genus+Innovus+SyntheticLib45nm. So, I have a list of files and during Elaboration phase I'm getting the following error (besides the amount of Wanings of size Mismatch):

Error : Cannot instantiate a blackbox interface. [CDFG-443] [elaborate]
: Port 'instr_if' of interface type 'AXI_BUS' in file '../src/ariane.sv' on line 41.

Did I forgot any file to add in the synthesis list?

My file list being used by synthesis, form my scripts:
../include/ariane_pkg.sv
../include/nbdcache_pkg.sv
../src/util/instruction_tracer_if.sv
../src/util/instruction_tracer_pkg.sv
../src/ariane.sv
../src/alu.sv
../src/branch_unit.sv
../src/btb.sv
../src/commit_stage.sv
../src/compressed_decoder.sv
../src/controller.sv
../src/csr_buffer.sv
../src/csr_regfile.sv
../src/decoder.sv
../src/ex_stage.sv
../src/fetch_fifo.sv
../src/fifo.sv
../src/id_stage.sv
../src/if_stage.sv
../src/instr_realigner.sv
../src/issue_read_operands.sv
../src/issue_stage.sv
../src/load_unit.sv
../src/lsu.sv
../src/lsu_arbiter.sv
../src/mmu.sv
../src/mult.sv
../src/pcgen_stage.sv
../src/ptw.sv
../src/scoreboard.sv
../src/store_buffer.sv
../src/store_unit.sv
../src/tlb.sv
../src/debug_unit.sv
../src/nbdcache.sv
../src/miss_handler.sv
../src/cache_ctrl.sv
../src/perf_counters.sv
../src/regfile.sv
../src/axi2per/axi2per.sv
../src/axi2per/axi2per_req_channel.sv
../src/axi2per/axi2per_res_channel.sv
../src/axi_node/defines.v
../src/axi_node/apb_regs_top.sv
../src/axi_node/axi_AR_allocator.sv
../src/axi_node/axi_AW_allocator.sv
../src/axi_node/axi_ArbitrationTree.sv
../src/axi_node/axi_BR_allocator.sv
../src/axi_node/axi_BW_allocator.sv
../src/axi_node/axi_DW_allocator.sv
../src/axi_node/axi_FanInPrimitive_Req.sv
../src/axi_node/axi_RR_Flag_Req.sv
../src/axi_node/axi_address_decoder_AR.sv
../src/axi_node/axi_address_decoder_AW.sv
../src/axi_node/axi_address_decoder_BR.sv
../src/axi_node/axi_address_decoder_BW.sv
../src/axi_node/axi_address_decoder_DW.sv
../src/axi_node/axi_multiplexer.sv
../src/axi_node/axi_node.sv
../src/axi_node/axi_node_wrap.sv
../src/axi_node/axi_node_wrap_with_slices.sv
../src/axi_node/axi_regs_top.sv
../src/axi_node/axi_request_block.sv
../src/axi_node/axi_response_block.sv
../src/axi_slice/axi_ar_buffer.sv
../src/axi_slice/axi_aw_buffer.sv
../src/axi_slice/axi_b_buffer.sv
../src/axi_slice/axi_buffer.sv
../src/axi_slice/axi_r_buffer.sv
../src/axi_slice/axi_slice.sv
../src/axi_slice/axi_slice_wrap.sv
../src/axi_slice/axi_w_buffer.sv
../src/axi_mem_if/src/axi2mem.sv \

The whole log it is the following:
elaborate $DESIGN
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'NONE' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LOAD' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'STORE' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ALU' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CTRL_FLOW' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MULT' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CSR' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 83.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ADD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 91.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SUB' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 91.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ADDW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 91.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SUBW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 91.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'XORL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 93.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ORL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 93.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ANDL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 93.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SRA' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SRL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SLL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SRLW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SLLW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SRAW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LTS' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LTU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'GES' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'GEU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'EQ' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'NE' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'JALR' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 99.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SLTS' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 101.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SLTU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 101.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MRET' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SRET' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ECALL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'WFI' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'FENCE' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'FENCE_I' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SFENCE_VMA' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CSR_WRITE' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CSR_READ' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CSR_SET' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CSR_CLEAR' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LWU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LH' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LHU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SH' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LB' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SB' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LBU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_LRW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 107.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_LRD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 107.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_SCW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 107.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_SCD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 107.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_SWAPW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ADDW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ANDW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ORW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_XORW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MAXW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MAXWU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MINW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MINWU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_SWAPD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ADDD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ANDD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ORD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_XORD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MAXD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MAXDU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MIND' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MINDU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MUL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 111.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MULH' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 111.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MULHU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 111.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MULHSU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 111.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MULW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 111.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'DIV' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'DIVU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'DIVW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'DIVUW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'REM' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'REMU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'REMW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'REMUW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 114.
Info : Elaborating Design. [ELAB-1]
: Elaborating top-level block 'ariane' from file '../src/ariane.sv'.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'NONE' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LOAD' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'STORE' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ALU' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CTRL_FLOW' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MULT' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 82.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CSR' [4] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 83.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ADD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 91.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SUB' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 91.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ADDW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 91.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SUBW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 91.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'XORL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 93.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ORL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 93.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ANDL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 93.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SRA' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SRL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SLL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SRLW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SLLW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SRAW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 95.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LTS' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LTU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'GES' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'GEU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'EQ' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'NE' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 97.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'JALR' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 99.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SLTS' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 101.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SLTU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 101.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MRET' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SRET' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'ECALL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'WFI' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'FENCE' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'FENCE_I' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SFENCE_VMA' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CSR_WRITE' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CSR_READ' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CSR_SET' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'CSR_CLEAR' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 103.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LWU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LH' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LHU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SH' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LB' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'SB' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'LBU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 105.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_LRW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 107.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_LRD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 107.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_SCW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 107.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_SCD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 107.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_SWAPW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ADDW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ANDW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ORW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_XORW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MAXW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MAXWU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MINW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MINWU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 108.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_SWAPD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ADDD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ANDD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_ORD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_XORD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MAXD' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MAXDU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MIND' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'AMO_MINDU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 109.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MUL' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 111.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MULH' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 111.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MULHU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 111.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MULHSU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 111.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'MULW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 111.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'DIV' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'DIVU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'DIVW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'DIVUW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'REM' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'REMU' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'REMW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 113.
Info : Bitwidth mismatch in assignment. [CDFG-372]
: Width of left hand side 'REMUW' [7] doesn't match the width of right hand side [32] in assignment in file '../include/ariane_pkg.sv' on line 114.
Error : Cannot instantiate a blackbox interface. [CDFG-443] [elaborate]
: Port 'instr_if' of interface type 'AXI_BUS' in file '../src/ariane.sv' on line 41.
Info : Deleting HDL design. [CDFG-305]
: Design 'ariane'.
Info : Error in Elaborating Design. [ELAB-4]
: Module 'ariane' contains errors and cannot be elaborated.
1

Cache coherence during a flush

There are some issues with the cache control:

• The cache control block should not serve a request if the cache is being flushed.
• A flush should reinitialize the cache, so the next requests are fetched from memory.

Error in "make sim"

Hi,

I am getting following error in "make sim" in the transcribt window of questasim:

 do tb/wave/wave_core.do
 ** Error: (vish-4014) No objects found matching '/core_tb/dut/i_frontend/*'.
 Error in macro ./tb/wave/wave_core.do line 3
 (vish-4014) No objects found matching '/core_tb/dut/i_frontend/*'.
     while executing
 "add wave -noupdate -group frontend /core_tb/dut/i_frontend/*"

Can you please help me with that?
Tobi

Single-stepping bug ?

I am detecting symptoms of a problem with single-stepping a program which works fine when run in one go. The symptom is that normal instructions work but branch and jump instructions always keep going to the next instruction in line regardless. If this is a true bug, can you confirm or suggest where in the code I should look to diagnose the problem?

[VCS] VCS doesn't support program inside module

We should move the code in the test-harness, or at least think about it a bit more...

Flush multiplication unit

Currently the multiplication/division unit is not flushed when the controller changes control flow. This needs a fix asap.

Load requests not being killed after a flush

A high kill_req_i should kill the load requests for the cache_ctrl no matter what state it is currently in. In the current version, some states of cache_ctrl are not sensible to kill_req_i.

In my case, the request was not killed and a speculative load that was issued before a flush wrote the scoreboard after the flush, but with a wrong pre-flush transaction id.

Deadlock on uncached write

When writing to memory which outside the cacheable range, this will be served by axi_adapter in miss_handler.sv, but it will be a single write. In the example wrapper, ariane_wrapped.sv, writes are consumed by axi2mem.sv which remains in state WRITE until the last (and only) word is indicated using slave.w_last (actually bypass_if.w_last), likewise axi_adapter remains in state WAIT_B_VALID until axi2bus reaches state SEND_B. However in SINGLE_REQ mode w_last is never set so we have deadlock.

I propose the following patch which prevents the deadlock, I do not know if is functionally correct:

diff --git a/src/miss_handler.sv b/src/miss_handler.sv
index 0c300a9..f494ba6 100644
--- a/src/miss_handler.sv
+++ b/src/miss_handler.sv
@@ -765,7 +765,7 @@ module axi_adapter #(
                             gnt_o = axi.aw_ready & axi.w_ready;
                             gnt_id_o = id_i;
                             case ({axi.aw_ready, `axi.w_ready})`
-                                2'b11: state_d = WAIT_B_VALID;
+                                2'b11: begin state_d = WAIT_B_VALID; axi.w_last = 1'b1; end
                                 2'b01: state_d = WAIT_AW_READY;
                                 2'b10: state_d = WAIT_LAST_W_READY;
                                 default: state_d = IDLE;

About ECC

Greetings,

I am curious whether you guys implement any ECC for srams used by Ariane Core. I did not see any module about error correcting. If you did, is there any chance your ECC module is open sourced?

Reserved instruction form C.JR (rs1=0) does not generate illegal instruction exception

Reserved instruction form C.JR (rs1=0) does not generate illegal instruction exception

error in "make build"

Hi,
I am getting following error when I do "make build"

vopt +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive -work work  core_tb -o core_tb_optimized +acc -check_synthesis
** Error: tb/core_tb.sv(132): Expected an interface instance as an actual for 'master'.
** Error: tb/core_tb.sv(132): Expected an interface instance as an actual for 'slave'.
Optimization failed
make: *** [build] Error 2

Can you help me with this error?

Thanks in advance.

Farhad

Issue while compile and link of ceil,scanf ,free or malloc function in C

Hi i am facing this issue when trying to run functions that are not defined in the syscalls.c file.

But the issue is actually telling me that this is a memory displacement issue. Is there a way to solve this problem?

So is it like the riscv-tools/riscv-tests/benchmarks/common/syscalls.c contains only certain limited functions like printf and string related functions. If in case i need to run some data structures then should i modify the syscalls according to my need?

Build error on VCS

I got a problem to build the ariane RTL code on VCS. It happens on the miss_handler.sv line #684,

#683:    // counter for AXI transfers
#684:    logic [$clog2(DATA_WIDTH/64)-1:0] cnt_d, cnt_q;
#685:    logic [(DATA_WIDTH/64)-1:0][63:0] cache_line_d, cache_line_q;

Here is the patch,

#684:    logic [ADDR_INDEX-1:0] cnt_d, cnt_q;

Memory Failure

# UVM_INFO @ 0: reporter [Program Loader] tohost: 0000000080001000 begin_signature 0000000080003000
# 
# UVM_INFO @ 0: reporter [RNTST] Running test core_test...
# [TRACER] Output filename is: trace_core_00_0.log
# UVM_INFO tb/env/core/core_eoc.svh(59) @ 371570000: uvm_test_top.m_env.m_eoc [Core Test] *** SUCCESS *** (tohost = 0)
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1268) @ 371570000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# 
# --- UVM Report Summary ---
# 
# ** Report counts by severity
# UVM_INFO :    7
# UVM_WARNING :    0
# UVM_ERROR :    0
# UVM_FATAL :    0
# ** Report counts by id
# [Core Test]     1
# [Program Loader]     2
# [Questa UVM]     2
# [RNTST]     1
# [TEST_DONE]     1
# ** Note: $finish    : /net/home/merchantf/Downloads/ModelSim-installation/mentor/2016-17/RHELx86/QUESTA-CORE-PRIME_10.5c-4/questasim/linux_x86_64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
#    Time: 371570 ns  Iteration: 50  Instance: /core_tb/tb
# End time: 11:24:02 on Mar 08,2018, Elapsed time: 0:00:07
# Errors: 2, Warnings: 0

Any idea why do I get into memory failure for "rv64um-v-divu"?

mibench and linux

Excuse me，I would like to ask a question about ariane

Is it possible to run linux on ariane now, can I use MiBenc to test ariane?

Thanks, wish all the best.