Topic: pll Goto Github
Some thing interesting about pll
Some thing interesting about pll
pll,<Pll/> React Programming Language Logo Component.
User: abranhe
Home Page: https://languages.abranhe.com
pll,Firmware (Sketch) for Arduino MEGA DDS (Direct Digital Synthesis) Analog Devices AD9915 Arduino Shield by GRA & AFCH
User: afch
Home Page: https://www.gra-afch.com
pll,PLL Simulator in SystemC-AMS
User: americodias
Home Page: https://americodias.com/docs/systemc-ams/pll.md
pll,Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.
User: charkster
pll,Guitar triggered PLL Synth effect
User: cracked-machine
pll,Digital Frequency Synthesizer with PIC16F88 and CD4046.
User: electronicayciencia
Home Page: https://electronicayciencia.com/2020/09/sintetizador-de-frecuencias-digital-con.html
pll,This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.
User: eyantra698sumanto
pll,Design and generate the GDSII file for an 8x PLL Clock Multiplier IP with open source PDK & tools
User: fahr-khadija
pll,Ein alternativer Elektronik-Adventskalender für das Jahr 2023
User: frifle
Home Page: https://frifle.github.io/adventskalender/
pll,8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
User: hiiask
pll,Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
User: idoka
Home Page: http://idoka.ru/my-fpga-and-asic-scripts/
pll,A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
User: infini8-13
pll,Source and support for the UXFFront module revision-T (TX/RX) for the ICOM IC-900/IC-901 UX radio modules
User: ke0ff
pll,8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
User: lakshmi-sathi
pll,LM7001 to Si4703 FM tuner bridge
User: lmartorella
pll,A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
Organization: merledu
pll,This code example demonstrates usage of AVR128DB48 microcontroller to generate 48MHz clock signal using PLL and OSCHF. In this code example, use of Timer/Counter type D (TCD) peripheral to realize peripheral clock frequency of 48MHz is demonstrated.
Organization: microchip-pic-avr-examples
pll,Sensorless FOC (PLL estimator) of AC induction motor with field weakening
Organization: microchip-pic-avr-solutions
pll,This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
User: muhammadaldacher
Home Page: https://drive.google.com/open?id=1TUYCLbdZC5S4dQVAxZmoUjMQPiLFntPe
pll,This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
User: muhammadaldacher
pll,All digital lowpas delta-sigma modulator (+digital up-converter) tune to fmax = 9 MHz
User: oliviercotte
pll,This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
User: parasgidd
pll,Library for the Si5351A (10 MSOP - 3 Clocks Only) clock generator IC in the Arduino environment , based on NT7S library.
User: pu2reo
pll,FOC driver library written in Rust
User: qff233
pll,iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
User: r4d10n
pll,Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process
User: ranjith-dhananjaya
pll,Rubik's cube solver using CFOP
User: saiakarsh193
pll,Bash scipt for loading AD9547/AD9548 configuration (.stp) via I2C
User: sanchox
pll,This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
User: sascha-kirch
pll,MC145192 PLL synthesizer control library for Arduino
User: sh123
pll,Self consistent model based filter design for 3-phase PLLs.
User: sjain-stanford
pll,Train your PLL skills on Rubik's cube with this groovy script
User: smonteillet
pll,Programming Languages Lab - IITG'2020
User: sravi1210
pll,Very minimalistic 20meter transceiver Digital Frequency Synthesizer with 0.96 or 1.3 inch 128x64 OLED Display for Ham-radio use
User: sv1onw
pll,Modified version of Si5351_OLED_DFS for simple CW TX use or DC receiver.
User: sv1onw
pll,This repository presents design of on-chip clock multiplier(8X PLL) using open source EDA tool OSU 180nm technology node
User: tejokrishna10
pll,Module for AOM-based modulation transfer spectroscopy (MTS) signal generation.
Organization: tu-darmstadt-apq
pll,Single-Phase PLL / Second-Order Generalized Integrators Phase Lock Loop
User: xiangyyang
pll,Using ADF4351/PLL to get the frequency you want by STM32F103 !
User: yongxiang-guo
pll,Support files for blog posts of Zurich Instruments
Organization: zhinst
Home Page: https://blogs.zhinst.com/
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