Topic: ip-core Goto Github
Some thing interesting about ip-core
Some thing interesting about ip-core
ip-core,The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example
User: alexo-git
ip-core,📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
User: esynr3z
ip-core,A custom UART IP core. Wrting to bare metal I/O pins independent of the FPGA model.
User: florianfrank
ip-core,Microarquitecturas y Softcores - CESE - FIUBA
User: gonzafernan
ip-core,Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
User: idoka
Home Page: http://idoka.ru/crypto-ip-core-gost-28147-89/
ip-core,Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
User: idoka
Home Page: http://idoka.ru/crypto-ip-core-gost-r3412-2015/
ip-core,Artículos escritos en base al Proyecto Final de la carrera Ingeniería en Computación FCEFyN UNC
Organization: jnonino-crpisetta-icomp
ip-core,Código Verilog y C realizado para la tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
Organization: jnonino-crpisetta-icomp
ip-core,Informe de la Tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
Organization: jnonino-crpisetta-icomp
ip-core,Implementation of a Tensor Processing Unit for embedded systems and the IoT.
User: jofrfu
ip-core,RGB PWM LED Demo project running on ARTY Z7-20 hardware
User: magictaler
Home Page: http://magictale.com/3718/arty-z7-zynq-7020-hello-world/
ip-core,A Python-based IP Core Management Infrastructure.
User: paebbels
ip-core,DisplayPort IP-core
User: parretto
ip-core,USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
User: rohitk-singh
ip-core,Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
User: rubinsteina13
Home Page: https://en.wikipedia.org/wiki/Alpha%E2%80%93beta_transformation
ip-core,Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
User: rubinsteina13
Home Page: https://www.xilinx.com/support/documentation/application_notes/xapp154.pdf
ip-core,Synthesizable SystemVerilog IP-Core of the I2S Receiver
User: rubinsteina13
ip-core,UART IP-core for FPGA.
User: sbaldzenka
ip-core,IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
User: vedranmv
ip-core,FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器,可实现视频压缩。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-MPEG2-encoder
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